Fg2 fdim surrogate routed

FG2 FDIM Surrogate Hardware

A carrier/backplane KiCad project that hosts four prefab modules (WeAct STM32F412RET6 Core Board, MCP2551 CAN breakout, LD24AJTA LED driver, two adjustable buck converters) and wires them into the Ford FG2 Falcon keypad/CAN harnesses the firmware in src/Keypad and src/Core targets.

Included files

• fg2_fdim_surrogate.kicad_pro – KiCad project file
• fg2_fdim_surrogate.kicad_sch – schematic, ERC-clean, netlist independently verified against the source data in gen_sch.py
• fg2_fdim_surrogate.kicad_pcb – PCB: all footprints placed, full netlist assigned, zero DRC errors. Copper routing is not done — see "Status" below.
• gen_sch.py / gen_pcb.py – the actual source of truth. Both files are generated from these scripts (data-driven component/net lists that import real KiCad library symbols/footprints). Re-run them after changing any pin mapping rather than hand-editing the .kicad_sch/.kicad_pcb s-expressions — see their docstrings for two non-obvious KiCad coordinate conventions they had to reverse-engineer and work around.
• DESIGN_NOTES.md – sourced facts about each prefab module, firmware/ hardware pin-mapping conflicts found (and not silently resolved) during this design, and open TODOs before fabrication.

Status

• Schematic: complete and verified — zero ERC violations, and every net cross-checked programmatically against the netlist export (not just "ERC is quiet," which turned out to hide real pin-swap bugs earlier in this design's history — see gen_sch.py's combine_y() docstring).
• PCB: footprints placed with real clearances (zero DRC violations), full netlist assigned (the ratsnest shows every connection this design needs), board outline, 4 mounting holes, and an unfilled GND copper pour on the back layer.
• Not done: copper routing. Even pins that look trivially adjacent turned out to share a column with other nets' pins in between on the THT header footprints — a straight trace risks shorting through the intervening pad. Doing this correctly needs real clearance-aware pathfinding (what pcbnew's interactive router is for), not blind text-generated line segments. Open the board in pcbnew, Fill Zones first (clears most of the GND ratsnest immediately), then route the remaining nets interactively.
• J3/J4 (WeAct P1/P2 socket spacing) use a placeholder center-to-center distance — WeAct's published pin tables don't include the physical board width. Verify against the real WeAct Core Board before fabricating.