BarelyScope

BarelyScope

BarelyScope is a compact, ultra-budget 2-channel digital oscilloscope based on the STM32F432CEU6 microcontroller. Designed within a compact 90 mm × 90 mm form factor, it features a built-in 1.8" color TFT display (ST7735R), dual BNC signal inputs, onboard controls, LED status indicators, and PC data streaming over USB.

📸 Visual Overview

Top 3D Render	Bottom 3D Render

PCB Layout	Circuit Schematic

Key Features

• Microcontroller Core: High-performance 32-bit ARM Cortex-M MCU (STM32L432KCU6 / STM32F432CEU6).
• Dual Channel Input: Standard female BNC connectors (CH1 and CH2) for probe hookup.
• Input Voltage Range: 0V to 3.3V native DC input range.
• Bandwidth & Sampling: Designed for bandwidth accurate up to 500 kHz.
• Onboard Graphical Display: 1.8" SPI TFT LCD powered by the ST7735R driver chip for real-time waveform rendering.
• PC Connectivity & Logging: USB Type-C connector with data streaming and logging capability to host software.
• Compact Form Factor: Tight 9 cm × 9 cm board dimensions, ideal for portable desktop use or field testing.
• Physical User Controls: Dedicated tactile push-buttons for Channel 1 select, Channel 2 select, and Record/Pause logging.
• Status LED Matrix: Visual feedback indicators for Channel 1 activity, Channel 2 activity, and active recording mode.
• 4-Layer PCB Stackup: Engineered for signal integrity and low noise distribution.

PCB Layer Stackup

BarelyScope utilizes a standard 4-layer PCB manufacturing stackup to ensure stable ground references and clean power distribution:

┌─────────────────────────────────────────────────────────────┐  Top Layer
│ Layer 1: Top Signal / High-Speed Traces & Components        │  (SIG)
├─────────────────────────────────────────────────────────────┤
│ Layer 2: Solid Ground Plane                                 │  (GND)
├─────────────────────────────────────────────────────────────┤
│ Layer 3: Power Rails (+3.3V)                                │  (PWR)
├─────────────────────────────────────────────────────────────┤
│ Layer 4: Bottom Signal / Secondary Ground Plane             │  (GND/SIG)
└─────────────────────────────────────────────────────────────┘  Bottom Layer

Hardware Specifications

Known Issues & Revision 2.0 Roadmap

While Revision 1.0 serves as an initial functional hardware prototype, several critical schematic and layout shortcomings were identified during design review. These items are tracked for correction in Revision 2.0:

1. Analog Front-End (AFE) Clamping & Protection

• Current Bug: BNC central signal pins connect directly to MCU analog inputs (PA0, PA1) without attenuation, current limiting, or ESD clamping. Voltages outside 0V–3.3V or static discharges will permanently damage the microcontroller.
• Rev 2.0 Fix: Implement a dedicated input protection network per channel:
  • Series current-limiting resistor ($1 ext{ k}\Omega$).
  • Dual Schottky ESD diode array clamped to 3.3V and GND (e.g., BAT54S).
  • Low-pass RC filter for anti-aliasing.
  • Future Expansion: Active Op-Amp buffer stage to raise input impedance to standard $1 ext{ M}\Omega$.

2. TFT Backlight Current Limiting

• Current Bug: The backlight power pin (LED+) on the TFT header (LCD1) is tied directly to +3.3V without a current-limiting resistor, risking excessive current draw or LDO overload.
• Rev 2.0 Fix: Place an inline current-limiting resistor ($10\Omega - 47\Omega$) or an NPN/MOSFET transistor circuit for PWM-controlled brightness.

3. Analog Supply Noise Filtering (VDDA / VREF+)

• Current Bug: The analog supply pin (VDDA/VREF+, Pin 5) shares the digital +3.3V power plane directly without LC/RC filtering, introducing digital switching noise into ADC measurements.
• Rev 2.0 Fix: Isolate VDDA from +3.3V via a ferrite bead and dedicated $100 ext{ nF} + 1\mu ext{F}$ decoupling capacitors placed directly adjacent to Pin 5.

4. SWD Header Footprint Reduction

• Current Bug: The SWD debugging connector (J2) uses a 14-pin pitch header, taking up excessive PCB real estate.
• Rev 2.0 Fix: Replace J2 with a standard 5-pin $2.54 ext{ mm}$ single-row header (3.3V, SWDIO, SWCLK, GND, NRST) or a compact 6-pin Tag-Connect footprint.