All Bloks of project

BitForge SDR

Pure Signal. Full Control.
Open-Source 16-bit Direct-Sampling HF SDR Transceiver | 9 kHz -- 72 MHz | >100 dB Dynamic Range

A high-performance Software Defined Radio transceiver built around the LTC2209 16-bit 153.6 MSPS ADC and MAX5885 16-bit DAC. Designed for demanding HF reception from VLF through the 4-meter band, with full transmit capability and instrumentation-grade dynamic range.

Note: This project is under active development. The hardware design (schematics + PCB) is complete. FPGA firmware is in progress.

Key Specifications

Why This Project?

16-bit at 153.6 MSPS -- wider Nyquist than LTC2208 designs

Most open-source direct-sampling SDRs use the LTC2208 (130 MSPS). The LTC2209 pushes the sample rate to 153.6 MSPS, extending the Nyquist bandwidth to 76.8 MHz and comfortably covering the entire 9 kHz -- 72 MHz range without aliasing concerns at the band edges.

Dual Digital Step Attenuators with 0.25 dB resolution

Two PE43711A DSAs in cascade provide 63.5 dB of digitally controlled attenuation in 0.25 dB steps. This is finer than most SDR designs (which use 0.5 dB or 1 dB steps) and enables precise AGC control from the FPGA without sacrificing signal quality.

LTC6432 combined LNA/ADC driver -- a unique topology

Instead of the traditional separate-LNA-plus-ADC-driver chain (PGA-103 + ADA4937 or similar), this design uses the LTC6432-15 as a combined low-noise amplifier and differential ADC driver. The result is a simpler signal path with +15.2 dB fixed gain, 3.0 dB noise figure, and +33 dBm OIP3 -- all in a single IC with dual-balun impedance matching.

7-band switched filter bank + wideband master LPF

Two PE42582A SP8T switches route the signal through one of seven optimized bandpass filters (90 kHz -- 73 MHz) or a wideband master LPF covering the full 9 kHz -- 72 MHz range. The master LPF provides a panoramic view of the entire HF spectrum for digital waterfall display, while the BPFs deliver sharp selectivity when zoomed into a specific band.

Si5391B integer-mode clock -- zero fractional spurs

The clock synthesizer operates in pure integer mode: 38.4 MHz TCXO x4 = 153.6 MHz. No fractional dividers means zero fractional spurs on the SDR waterfall -- a real advantage over designs using fractional-N PLLs with 25 MHz references. Clock jitter is below 50 fs RMS, preserving the full 16-bit ADC performance.

Full transmit path with 16-bit DAC

The MAX5885 16-bit DAC shares the same signal chain (filter bank, LTC6432, and RF switches) in reverse for TX. Atomic RX/TX switching is controlled by a single FPGA pin with <100 ns transition time -- no sequencing logic required.

Extended range: 9 kHz -- 72 MHz

Coverage extends from VLF (9 kHz) through the entire HF spectrum and up to the 4-meter band (70 MHz). The 3-stage RF choke network in the LNA power supply is specifically designed for continuous performance from 9 kHz to 72 MHz without resonant dips.

Comparison with Existing SDR Platforms

Architecture

                            ┌─────────────────────────────────┐
                            │        FPGA (Zynq US+)          │
                            │   ALINX AXU2CGB via J701/J901  │
                            │                                 │
                            │  J701: ADC LVDS (17 diff pairs) │
                            │  J901: DAC data + control (3.3V)│
                            └──┬──────────────┬───────────────┘
                               │              │
                          ADC LVDS        DAC data + /RX_TX_MODE
                               │              │
┌─────────┐   ┌─────────┐   ┌─┴──────┐   ┌───┴──────┐
│ SMA RX  │   │Block 1  │   │Block 7 │   │ Block 9  │
│  Input  ├──►│DSA1     │   │LTC2209 │   │ MAX5885  │
│  (J101) │   │0-31.75dB│   │ADC     │   │ DAC      │
└─────────┘   └────┬────┘   └───▲────┘   └────┬─────┘
                   │             │              │
              ┌────▼─────────────┴──────────────┴────┐
              │          Block 4: RF Switches         │
              │       3x F2912 (atomic RX/TX)         │
              │  RX: Antenna→ADC  TX: DAC→Antenna     │
              └────────────────┬──────────────────────┘
                               │
                   ┌───────────▼───────────┐
                   │  Block 6: LTC6432     │

Signal flow (RX): Antenna → ESD protection → Balun → DSA1 → Filter Bank → DSA2 → LTC6432 → RF switches → LTC2209 ADC → LVDS → FPGA

Signal flow (TX): FPGA → MAX5885 DAC → RF switches → Filter Bank → DSA2 → LTC6432 → RF switches → Antenna

Repository Contents

Getting Started

Prerequisites

• KiCad 8.0 or later -- https://www.kicad.org/download/
• A web browser (for the interactive BOM)

Viewing the Design

1. Schematics: Open schematics/All_Bloks_of_project.kicad_pro in KiCad. The top-level schematic contains all 9 functional blocks with hierarchical sheets.

2. PCB Layout: Open the same project file and switch to the PCB editor, or open schematics/All_Bloks_of_project.kicad_pcb directly.

3. Interactive BOM: Open schematics/bom/ibom.html in any web browser. This provides a visual, searchable component placement overlay on the PCB -- no KiCad installation required.

4. Production files: The schematics/production/ directory contains ready-to-order Gerber files and BOM.

FPGA Platform

This board connects to the ALINX AXU2CGB carrier board (Xilinx Zynq UltraScale+ XCZU2CG) via two 2x20 pin headers:

• J701 (mapped to ALINX J12): ADC LVDS interface -- 16 data pairs + 1 clock pair
• J901 (mapped to ALINX J15): DAC data bus + control signals (3.3V LVCMOS)

See ALINX_Interface_Pinout_Specification.md for the complete pin mapping.

License

This project is licensed under the CERN Open Hardware Licence Version 2 -- Strongly Reciprocal (CERN-OHL-S v2).

See the LICENSE file for the full text.