Xiao c3-ir rf

flow-tap interposer — KiCad project

Buffers the stock GICAR flow-meter pulse into ito, in-line and reversible. Design rationale + install steps are in the project doc: 06-015. Topology picture: flow-interposer.svg.

Status (2026-07-13): routed + DRC-clean, fab-ready. The board is generated headlessly (generate_pcb.py, kiutils) and validated with kicad-cli (DRC: 0 violations, 0 unconnected). Gerbers/drill are exported in flow-tap-gerbers.zip; a top render is flow-tap-top.png. Board size ≈ 23.1 × 19.8 mm, 2-layer.

Open flow-tap.kicad_pcb in KiCad for a final eyeball before ordering (mains-adjacent signal). The placement is functional but roomy — you may want to compact it and/or swap the vertical XH headers for right-angle (S…-XH-A) so the cables exit the board edges.

Connectors (resolved)

All three ports are JST XH, 2.5 mm (the GICAR board connector measures 2.0 mm between pins → 2.5 mm pitch; ito's IMPULSE side is XH too).

The +14.3 V (J1.2/J2.2) passes J1→J2 only and never reaches J3. J3 taps J1.4/J2.4 (signal) buffered through U1, referenced to the shared GND.

Components

U1 (SN74LVC1G17, DBV/SOT-23-5) pins: 1 NC · 2 A(in) · 3 GND · 4 Y(out) · 5 VCC (per the TI datasheet).

Nets

  N_PLUS (14.3 V) : J1.2 — J2.2                              [pass-through ONLY]
  GND             : J1.3 — J2.3 — J3.1 — U1.3 — C1.2         [B.Cu network]
  N_O    (pulse)  : J1.4 — J2.4 — U1.2 (A input)
  V5     (ito 5V) : J3.3 — U1.5 (VCC) — C1.1
  N_OUT  (buffer) : U1.4 (Y) — J3.2

Signals route on F.Cu; GND routes on B.Cu (own layer → never crosses a signal). No copper pour is used, so there is no zone-fill step.

Regenerate / validate / fab (headless)

# 1. generate the board (native, no KiCad needed)
python3 generate_pcb.py footprints flow-tap.kicad_pcb

# 2. validate + export with kicad-cli (KiCad 9; on Apple Silicon use the amd64 image)
docker run --rm --platform linux/amd64 -v "$PWD:/w" -w /w kicad/kicad:9.0 sh -c '
  kicad-cli pcb drc flow-tap.kicad_pcb
  kicad-cli pcb export gerbers -o gerbers/ flow-tap.kicad_pcb
  kicad-cli pcb export drill   -o gerbers/ flow-tap.kicad_pcb
  kicad-cli pcb render --side top -o flow-tap-top.png flow-tap.kicad_pcb'

footprints/ holds the four KiCad-9 footprints the generator places (so it runs without a local KiCad install).

Note: pcbnew Python scripting crashes under amd64 emulation on Apple Silicon (malloc(): unaligned tcache chunk), so this project generates with kiutils (pure Python, native) and only uses the compiled kicad-cli for DRC/export/render.

Order (JLC)

1. Upload flow-tap-gerbers.zip. Select 2-layer.
2. Enable SMT assembly (top only) and upload the BOM + CPL:
   • BOM: flow-tap-BOM.csv
   • CPL / pick-and-place: flow-tap-CPL.csv
3. Hand-solder the three JST-XH connectors (J1/J2/J3) — they're not in the BOM/CPL.
4. Piggyback on the plumb-in bracket order.

Assembly BOM (2 parts)

U1 (TI SN74LVC1G17DBVR) is an Extended part — the ~$3 one-time loading fee is worth it over hand-soldering a SOT-23-5. (If you'd rather avoid the fee, both parts are trivial to hand-solder; the 0603 is easy, the SOT-23-5 wants hot air or a steady hand — leave SMT assembly off and populate them yourself.)

⚠ Verify rotations in JLC's CPL preview before ordering. The CPL carries KiCad's rotations; the 0603 maps 1:1, but U1 (SOT-23-5) commonly needs a rotation offset to line pin 1 up with JLC's part orientation. JLC's online viewer overlays each part on its footprint — spin it there if it looks wrong.