Rl fc f405.routed

RL PCB — an AI design copilot for KiCad

RL PCB sits beside KiCad and works like a senior hardware engineer looking over your shoulder. You describe what you want to build; it helps you choose real parts from your KiCad libraries, works out the values, places the symbols for you, tells you exactly which pin connects to which pin, and then checks your wiring. It also helps with the board: stackup, net classes, placement, routing guidance, autorouting and DRC.

The division of labour is deliberate: language models are bad at drawing schematics (floating "ghost" wires, near-misses), so RL PCB never draws wires. You draw, and it does everything around the drawing: research, parts, numbers, placement, instructions, and verification.

 you ──► "I need a 24 V PLC input card with 8 isolated inputs"
          │
 RL PCB ─►│ requirements → architecture → datasheet/app-note research → reference designs
          │ → parts from YOUR libraries → calculated values → design plan (parts + nets)
          │ → plan review (ERC before drawing) → symbols placed (no wires)
          │ → "wire U3 pin 7 (OUT) to R12 pin 1 …" → you wire → verify: 87 % done,
          │   R14.2 not connected, ghost wire at (120.6, 88.9) mm → fix → 100 %
          │ → stackup + net classes → placement → routing guidance / autoroute → DRC → Gerbers

You choose how much the AI does

The engineer sets the AI's autonomy for each part of the design:

• teach: it explains.
• advise: it guides; you edit.
• propose: it prepares each change on a copy of the project, with the check results before and after, and you accept or reject it.
• do: it edits; every change is journalled and can be undone.

For example, the power block can be in "do" while the routing is in "advise". Every result says what the checks verified and what they could not, such as part data without a datasheet or EMC that was not simulated, so a weaker model's mistakes are caught where checks exist and flagged where they do not. See docs/COPILOT.md.

What's inside

Three ways to talk to it

1. Claude Desktop (works with your Claude Pro plan — no API key). The installer registers RL PCB as an MCP server; open Claude Desktop and all 90 tools are available. Say "Open my KiCad project in Documents\KiCad\myboard and help me design…".
2. The RL PCB panel inside KiCad. A toolbar button (PCB editor; also the schematic editor on KiCad 10) opens a chat panel. It needs either an Anthropic API key (Settings ⚙) or a local model through any OpenAI-compatible server (Ollama, LM Studio…).
3. Claude Code / any MCP client: claude mcp add rlpcb -- <venv python> -m rlpcb.agent.mcp_server.

Install (Windows)

Requirements: KiCad 8, 9 or 10 (9/10 recommended), Python 3.10+, Git (for the corpus), optionally Java 21 for autorouting.

cd path\to\rlpcb
powershell -ExecutionPolicy Bypass -File .\install_windows.ps1            # add -SeedCorpus to download reference designs

It creates .venv, installs mcp, kicad-python, pymupdf, indexes your libraries, installs the KiCad plugins into Documents\KiCad\<version>\, registers with Claude Desktop, makes a desktop shortcut, then runs python -m rlpcb doctor.

Then in KiCad 9/10: Preferences → Plugins → Enable KiCad API (for live highlighting and moves) and restart.

Linux/macOS: ./install.sh [--seed-corpus].

First session

You:     Open C:\Users\me\Documents\KiCad\plc_input and let's design an 8-channel 24 V digital input card
         for a Raspberry Pi CM5, IEC 61131-2 type 1, galvanically isolated.
RL PCB:  (asks about channel count, isolation voltage, connectors, power) … proposes architecture …
         searches the knowledge base (industrial_plc_io) and reference designs … calculates the input
         divider/current limiter … builds the plan … plan_review: 0 errors …
         places 41 symbols (Ctrl+V) … "Block 'input_ch1': 1) Draw a wire from J1 pin 1 at (25.4, 40.6) to
         R1 pin 1 at (38.1, 40.6) …"
You:     done with channel 1
RL PCB:  verify → 92 %: R3 pin 2 is not connected; the wire from U2 pin 3 ends 0.64 mm short of it
         (dangling end at 120.65, 88.90). Everything else in channel 1 matches the plan.

Command line

python -m rlpcb doctor                    # check everything
python -m rlpcb index [--force]           # (re)index libraries
python -m rlpcb check  path\to\project    # ghost wires & drawing problems
python -m rlpcb verify path\to\project    # schematic vs plan
python -m rlpcb nets   path\to\project [regex]
python -m rlpcb ingest-docs D:\Books\Electronics
python -m rlpcb corpus seed | owner/repo | D:\OpenHardware
python -m rlpcb tool <tool_name> '{"json": "args"}'
python -m rlpcb serve --open              # chat panel
python -m rlpcb mcp                       # MCP server (stdio)

Safety of your files

• Schematic/board edits are splices: the rest of the file stays byte-for-byte identical, the result is parsed before writing, and a timestamped backup goes to <project>\.rlpcb\backups\.
• If KiCad has the file open (lock file present), RL PCB warns you; clipboard mode and the live API avoid the conflict entirely.
• The autorouter writes <name>.routed.kicad_pcb, never your original.
• mech_export writes <board>.mech.json, which describes the board for the product around it: outline, holes, connectors with the edge they face, and part heights. mech_check checks the board against the enclosure.json that RL CAD writes. See ../rlcad/docs/INTEGRATION.md.
• finish_routing closes what the autorouter left (plane stitching, grid router, rip-up, negotiated congestion) and writes <name>.finished.kicad_pcb, checked with KiCad's own DRC after every step.
• The panel server only listens on 127.0.0.1 and rejects cross-origin requests. allow_file_writes=false in Settings makes RL PCB read-only.

Honest limits (and the roadmap)

• It will not draw wires, by design. Net labels on pin ends are offered for buses.
• The AI's design judgement is only as good as its research: it cites the knowledge base, the datasheet section and real reference designs, and you should still read the datasheet's typical-application circuit.
• Autorouting is for non-critical nets; power loops, high-speed and analog nets should be routed by hand with the guidance given.
• A Blackwell-class accelerator board (20+ layer HDI, ~1000 A core rail, PCIe Gen5/6) is not a first project; the gpu_accelerator_board architecture file lays out a realistic learning path toward it.

See docs/EVALUATION.md for how a small model performs with and without blocks, examples/drone_fc/ for a complete worked project (a drone flight controller, idea → routed board), docs/USER_GUIDE.md for the workflow in depth and docs/ARCHITECTURE.md for how it works.