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4 layers50 × 75 mmPhasedArray, the printed circuit board in 3D

This repository contains all the sources for a working ultrasonic phased array powered by a ZYNQ FPGA.

Size
50 × 75 mm
Copper layers
4
Thickness
1.6 mm
Parts
132
Nets
171
Pads
494
Tracks, vias
954, 247
Pours
3
Routed
Yes
KiCad
KiCad 6 (file 20211014)
Created
11 Oct 2022
Updated
1 May 2023

Overview

PhasedArray is an open-source printed circuit board by dylanmsu, from the dylanmsu/Ultrasonic_Phased_Array repository on GitHub, published under the GPL-2.0 licence. It is a 4-layer board of 50 × 75 mm with 132 parts on 171 nets, routed with 954 tracks and 247 vias.

It is built around the TC4428AEOA and 74AHCT595D. Its parts include 59 capacitors, 30 ICs, 16 resistors and 2 connectors. It belongs with the fPGA and programmable logic boards of this library.

Main components

2

README

README.md

Ultrasonic_Phased_Array

This repository is under construction and will contain all the sources for a working ultrasonic phased array. The vitis project in this repository is to be used in a accoustic levitation example.

Working principle

Lets consider an example where we want to send a single pulse of airpressure to a certain point in space. We have an array of transducers we can work with. Since the waves travel in a sphere around the transducers, we can time the pulses at each transducer in such a way that all the wavefronts arrive at the same time in a single focal point. This is illustrated in the animation below.

[blocked]

If we were to send a sinewave with the same delay through the transducers instead of a single pulse, all the peaks and troughs of those waves would ideally only add up in the focal point. The amplitude would then be the greatest at that point and ideally cancel out everywhere else. This is actually not always the case because a side effect of using a periodic signal is that we create te posibility of sidelobes. Sidelobes are areas where some of the sinewaves constructively add up unwantedly where the phase shift is a multiple of 360 degrees. To prevent the occurance of sidelobes, we need to space the transducers with a distance between 1/2 wavelength, and 1/4 wavelength.

To calculate the phase offsets per transducer for a single focal point, the following formula is used: $$\varphi = -\frac{2\pi\sqrt{(X_t - X_f)^2 + (Y_t - Y_f)^2 + (Z_t - Z_f)^2}}{\lambda}$$ Where:

  • $\varphi$ = the phase offset for a given transducer
  • $X_t, Y_t, Z_t$ = the location of the transducer
  • $X_f, Y_f, Z_f$ = the location of the focal point
  • $\lambda$ = wavelength

The waves exiting the transducers will look something like this.

[blocked]

The red dots at the bottom are sources emitting pure sinusodial signals with an adjusted phase delay so all the waves are in phase at the red dot around the middle.

There is an included python script called 'wave_equation.py' that focuses the waves to your mouse location by manipulating the phases of the emitters. It solves the 2d wave equation so it should be more acurate than the above animation.

We can also steer a beam into a specified direction. To do this we have to align the wavefronts into a plane where its normal vector points to the direction of travel. This is illustrated in 2d in the animation below.

[blocked]

Here the phase offsets are calculated using the following formula: $$\varphi = \frac{2\pi(aX_t+bY_t-Z_t)}{\lambda\sqrt{1+a^2+b^2}}$$ Where:

  • $\varphi$ = the phase offset for a given transducer
  • $X_t, Y_t, Z_t$ = the location of the transducer
  • $a$ = the slope of the tangent plane in the x-axis
  • $b$ = the slope of the tangent plane in the y-axis
  • $\lambda$ = wavelength

The waves exiting the transducers will look something like this.

[blocked]

In the case for this project, the spacing between the sources is 10 mm wich is more than double the recommended wavelength so we expect some loss of energy through sidelobes. Even more so diagonally since the sources are placed in a rectangular grid and the diagonal spacing is 14.14 mm. Placing the sources in a hexagonal grid solves big diagonal spacing but this makes the design of the PCB more challanging. For this reason i opted to design a rectangular grid of sources anyway.

Setup

There are two array's used in the levitation example. One is facing upwards and the other is facing downwards. They are facing eachother with a distance of 70mm. This distance is arbitrarily chosen based on the needed volume for levitation.

FPGA

The FPGA used in this project is the ZYNQ XC7Z020 on a Zybo Z7 board but any Zynq FPGA should work. The FPGA contains two distinct parts: The processing system (PS) and the programmable logic (PL):

Programmable Logic

The PL contains an implementation which receives 7 bit values from the PS (Processing System) for every transducer. This value sets the phase of the output signal. This is acheived by making a fifo of length = 2^7 in the case of a phase resolution of 7 bits. The 40KHz signal is fed into the fifo at 40KHz * 2^7 = 5.12MHz. The reason for this is because we want exactly 1 full period of the signal in the fifo. The 7 bit value determines at which address of the fifo the output signal is tapped from. This way wan can adjust the phase of the output signal in 2^7 steps per period.

The block diagram that takes an AXI peripheral bus and outputs a serial data stream to drive the included transducer board is illustrated below.

[blocked]

here is an overview of the in- and output signals:

  • signal_in: this is the signal that will drive the transducers and whos phase will be altered, in our case this signal would have a 50% dutycycle at 40KHz.
  • fifo_clk: this is the clock that shifts the fifo's used for the delay generation. This should be 2^7 times faster than the 40KHz signal. in this case the fifo length and so the phase resolution is 2^7. This means a frequency of 5.12MHz.
  • ser_clk: this is the serial clock that drives the serializer and also the shift registers on the transducer board. This clock should be 5x the 'fifo_clock' if each shift register drives 5 transducers. This means a frequency of 25.6MHz.
  • s00_axi_aclk: this is the AXI peripheral clock comming directly from the Processing system.
  • en: enable the output signal.
  • resetn: active low reset signal.
  • S00_AXI: AXI slave port
  • pmod_out: this port goes directly to a Pmod port on the FPGA-board and drives the transducer board.

The AXI peripheral IP_block generates the delayed signals and outputs them as a 25 bit vector. This vector is split into 5x 5 bit vectors by the xlslice blocks. The 5 bit vectors enter the seializer. The data is then clocked bit by bit to the output.

Implementation

[blocked]

TODO

Processing System

The Processing system sends data to the FPGA facric which adjusts the phase offsets of the physical transducers.

Practical limitations

In an ideal world the signal applied to the physical transducer should give the same signal in air pressure. That is however not the case. For every transducer there is a significant random phase shift present. This will completely negate our effort to acheive a phased array. So we have to measure the phase shift of every transducer and incorporate this into the phase calculations.

Video

Below is a video showing two ultrasonic arrays levitating a piece of styrofoam in an preprogrammed path. Watch the video

Parts

132
QtyValueFootprintReferences
30100nFCapacitor_SMD:C_0603_1608MetricC11, C13, C15, C17, C19, C21, C23, C25, C27, C29, C31, C33, C35, C37, C39, C41 +14
284.7uFCapacitor_SMD:C_0805_2012MetricC1, C2, C3, C10, C12, C14, C16, C18, C20, C22, C24, C26, C28, C30, C32, C34 +12
25Speaker_UltrasoundMA40S4R:XDCR_MA40S4RLS1, LS2, LS10, LS11, LS12, LS13, LS14, LS15, LS16, LS17, LS18, LS19, LS20, LS21, LS22, LS23 +9
25TC4428AEOATC4428AEOA:SOIC127P600X175-8NU1, U2, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U23 +9
1539RResistor_SMD:R_0402_1005MetricR2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16
574AHCT595Package_SO:TSSOP-16_4.4x5mm_P0.65mmU26, U27, U28, U29, U30
10RResistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolderR1
147uFCapacitor_SMD:C_Elec_5x5.4C59
1Conn_02x06_Odd_EvenConnector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_HorizontalJ2
1Screw_Terminal_01x02TerminalBlock_Phoenix:TerminalBlock_Phoenix_PT-1,5-2-3.5-H_1x02_P3.50mm_HorizontalJ3

Questions

How big is the PhasedArray PCB?

It measures 50 × 75 mm and has 4 copper layers, 1.6 mm thick.

What parts does the PhasedArray use?

132 parts, built around the TC4428AEOA and 74AHCT595D. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the PhasedArray KiCad files?

From the dylanmsu/Ultrasonic_Phased_Array repository on GitHub, at the commit this page was made from: the board is hardware/PhasedArray5x5/PhasedArray.kicad_pcb and its schematic hardware/PhasedArray5x5/PhasedArray.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the PhasedArray design in my own project?

Its repository publishes it under the GPL-2.0 licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).

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