Not module

kransputer

What Kransputer is

Kransputer is a working computer built from a few thousand discrete CMOS transistors — a machine on the scale of an Intel 4004, but made of parts you can hold — designed to grow into a multiprocessor: one core, then a ring of up to eight, passing messages the way INMOS's Transputer did. It exists to be understood and rebuilt, by a person, a class or a hackerspace. Not to be sold.

Why it looks the way it does

One decision forces everything else: CMOS. Almost every discrete-transistor computer ever built is NMOS and burns about a watt standing still. CMOS costs twice the transistors but makes power scale with clock rate instead — turn the clock down and the machine sips. Staying inside a small transistor budget is why the design is stripped to the bone:

• One instruction — subleq only, so there is no decoder. The instruction set lives in the assembler as macros.
• A few bits at a time — a serial datapath, so the arithmetic unit is a handful of adders. You pay in clock cycles, which are cheap.
• No bus — memory, display and input all speak SPI over four wires. No address bus, no data bus.

On this machine, talking to the core next door is cheaper than reading your own memory. That is why the ring is the point, not an afterthought.

How it gets built — from the ground up

The architecture is settled on paper: a SUBLEQ core with a serial datapath and SPI links, meant to grow into a message-passing ring. What is deliberate is the direction of the work. Instead of proving the whole machine on an FPGA before touching a soldering iron, Kransputer is built upward from real gates, one module at a time.

1. Gates — small PCBs, each a fistful of MOSFETs forming one logic function (NAND, NOR, NOT …), that plug into a breadboard and share a common bus. This is the layer built so far.
2. Blocks — those gates wired into the units the design calls for: the serial adder that is the whole ALU, the registers, the subleq sequencer and bit counter, the SPI interface to memory, the four-wire link to the next core. Each block is first modelled in structural Verilog — gate for gate, built from the same NAND/NOR/NOT cells as the boards — and checked in simulation, then built physically on breadboards.
3. A core — one complete processor, assembled from the blocks.
4. A ring — the core replicated and connected: two, then four, then eight, blocking on the links for synchronisation.

The structural model is the reference: the same stimulus into the simulation and into the breadboard must give the same result, or the block is wrong.

Status

The gate boards are drawn but not yet routed — schematics and rough placement are done, copper is not. Work right now is on the first blocks in structural Verilog, which land here soon. Once those hold up in simulation the boards get routed and finished for a first self-ordered run, with build notes and other material alongside.

This repository

Discrete-logic building blocks for the kransputer — the Gates layer above. Each module is a small PCB that plugs into a breadboard on two opposite edge headers carrying an identical 16-pin pass-through bus, so modules can sit side by side across one or more breadboards and be wired together into larger logic.

Boards

Logic FETs are AO3400A (N-channel) / AO3401A (P-channel) in SOT-23.

The logic boards carry no indicator parts. Every node is on the bus; the indicator board buffers each signal with a single AO3400A in common source (its gate is high-impedance, so the logic net is not loaded) that sinks an LED fed from the indicator board's own VDD rail. LED lit = logic 1. Watching the machine therefore does not sag the logic levels.

Bus pinout

Both edge headers (J1, J2) carry the same 16 pins, wired 1:1, so any signal is reachable from either edge. Framing is fixed: pin 1 = VDD, pin 2 = GND, pins 3–14 carry the 12 signal nets the board drives, pins 15/16 are the edge-to-edge spares (BUS_X, BUS_Y).

J1/J2 are stacking headers: male tails point down into the breadboard, female sockets face up so the indicator shield can plug onto the same 16 pins.

Signal nets per board (bus pins 3–14)

The bus is positional: J1 pin k ≡ J2 pin k on every board. The indicator shield taps pins 3–14 as SIG1..SIG12 and shows whatever a neighbouring board drives there.

Supply: 5 V on the bus. The two header rows are 0.9" apart (row a to row j of one breadboard); columns b–e and f–i stay free for patch wires.

Build

python3 -m venv venv
./venv/bin/pip install -r requirements.txt

./venv/bin/python circuit.py             # writes every <target>_module.net
./venv/bin/python circuit.py nand        # or just one

kicad_env.py finds the KiCad symbol libraries at the macOS bundle path (/Applications/KiCad/KiCad.app/...). On Linux or Windows, set the KICAD*_SYMBOL_DIR / KICAD*_FOOTPRINT_DIR environment variables to your install's library paths before running, or adjust kicad_env.py.

1. Turn the netlist into a board. Either open a new PCB project nand_module/ in KiCad and "Update PCB from Netlist", or run kinet2pcb headless (needs skidl, kinparse and pcbnew on the same Python — i.e. installed into KiCad's bundled Python, since pcbnew is not in the venv):

   kinet2pcb -i nand_module.net -o nand_module/nand_module.kicad_pcb -w --overwrite

2. Rough auto-placement — run from the folder that contains nand_module/, using KiCad's bundled Python:

   /Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/3.9/bin/python3 \
       place.py nand

   place.py positions J1/J2 on opposite 0.9" edges, clusters each gate between them, draws a tight Edge.Cuts rectangle and pours a B.Cu GND zone. Pass an explicit .kicad_pcb path as a second argument to place a board elsewhere.
3. Reopen in KiCad, nudge, route. Re-fill the GND zone. Run DRC.
4. Plot Gerbers.

Repeat with nor, not, and indicator (each is its own KiCad project in its own <target>_module/ folder). nand_module/, nor_module/, not_module/ and indicator_module/ are checked in.

Fan-out

A discrete gate output driving other gate inputs is limited by speed, not current (CMOS inputs are capacitive) — fine at this machine's speeds. One indicator-board channel adds roughly the AO3400A gate capacitance to the net it watches; one indicator board on the bus is negligible.

Tests

./venv/bin/pytest

The placement integration test is skipped unless kinet2pcb can import pcbnew (it cannot from the venv). place.py uses fixed, hand-computed coordinates per board type, so its output is deterministic and easy to eyeball in KiCad.

Layout

• circuit.py — SKiDL netlist generator (all boards, no arg = build every one)
• place.py — pcbnew layout: exact positions per board type, Edge.Cuts, GND pour
• kicad_env.py— points SKiDL at the bundled KiCad libraries on macOS
• SYMBOLS.md — resolved KiCad symbols (AO3400A/AO3401A, LED, R array, header)
• tests/ — SKiDL-netlist topology checks per board + CLI + place integration

Licence

PolyForm Noncommercial License 1.0.0. Build it, study it, modify it, teach with it, and contribute — freely, for any noncommercial purpose. Selling kits, boards, or hardware based on this work is reserved to the maintainer; see COMMERCIAL.md. Contribution terms are in CONTRIBUTING.md.