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4 layers65 × 56 mmCanary pwr, the printed circuit board in 3D

Four 25 F cells in series for CANary-PWR's LTC3350 hold-up, on a lead (design record: docs/CANary-PWR-Spec.md §P4). The board has no active parts: four cells, an NTC, two Kelvin net ties and a Micro-Fit 2 × 5 header.

Size
65 × 56 mm
Copper layers
4
Thickness
1.6 mm
Parts
132
Nets
127
Pads
498
Tracks, vias
1,397, 209
Pours
23
Routed
Yes
KiCad
KiCad 10.0 (file 20260206)
Created
11 May 2026
Updated
7 Nov 2026

Overview

Canary pwr is an open-source printed circuit board by danbrunski, from the danbrunski/canary repository on GitHub. It is a 4-layer board of 65 × 56 mm with 132 parts on 127 nets, routed with 1,397 tracks and 209 vias.

It is built around the STM32G031K8T6, TCAN1043HDQ1 and INA226AIDGSR, with the LM61460AASQRJRRQ1, LM74700QDBVTQ1 and LTC3350EUHF#PBF among its other parts. Its parts include 45 resistors, 44 capacitors, 8 ICs, 8 diodes and 8 transistors. It belongs with the STM32 boards of this library.

Main components

12

README

hardware/canary-capbank-rev1.0/README.md

CANary cap bank rev 1.0

Four 25 F cells in series for CANary-PWR's LTC3350 hold-up, on a lead (design record: docs/CANary-PWR-Spec.md §P4). The board has no active parts: four cells, an NTC, two Kelvin net ties and a Micro-Fit 2 × 5 header. It is 87 × 55.5 mm, 2 layers, 1.6 mm, 1 oz, with four M3 holes.

State 2026-10-20: ERC clean at every severity. DRC is clean with schematic parity and 0 unconnected, and via_in_pad.py reports 0. Both ends of the lead match its pin map (hardware/tools/check_capbank_lead.py).

Files

FileWhat
canary-capbank.kicad_{pro,sch,pcb}The project, generated. No hand edits yet, so gen/build.sh can regenerate them
BOM.csvThe board's parts, exported from the schematic
BOM-offboard.csvThe lead (from hardware/tools/capbank_lead.py, shared with CANary-PWR J4) and the fixings
lib/footprints.pretty/The cell laid flat, written by gen/footprints.py
lib/3dmodels/STEP models of the cell and the Micro-Fit header for KiCad's 3D viewer, written by hardware/tools/gen_3dmodels.py
gen/bank.py parts and nets, layout.py placement and copper, build.sh runs it all and the checks

gen/build.sh overwrites the KiCad files. Once the board is edited in KiCad, the board file becomes the source of truth and the generators stop being run on it, as with CANary-PWR.

Parts

  • Cells: Eaton TVA1625-3R0256-R, 25 F, 3.0 V rated, run at 2.5 V. It is the only candidate that meets all three requirements:

    • AEC-Q200;
    • holds 2.5 V at 85 °C (every 2.7 V cell is derated to 2.3 V there);
    • rated past the 4 A charge current (4.2 A at a 15 °C rise).

    It is long: 16.5 × 28.9 mm max. The footprint's envelope is Ø17 × 29 mm, so the alternate fits the same board: UCAP BCAP0025 P300 X11, 3.0 V, 4.1 A, not AEC-Q200. The operator confirmed every part here in stock at DigiKey, lead parts included (2026-10-20).

  • NTC: Vishay NTCS0603E3103FLT, 10 k 1 %, B25/85 3435 K, AEC-Q200. Murata NCU18XH103F6SRB and TDK NTCG163JF103FT1S follow the same curve within 0.3 % above 0 °C, so one GPI table in the firmware covers all three. TH1 sits on cell 1's − lead copper; Maxwell notes that a sensor on a terminal reads the cell accurately.

  • Connector: Molex 43045-1002, the gold version of 43045-1000 on the same footprint, on both boards (2026-10-20, when the tin -1000 went out of stock). Gold also resists fretting under vibration better than tin.

  • Lead: 172952-1001 housings with TPA (two 172953-1001 retainers each) and 43030-0009 gold crimps, 20 AWG, ≤ 300 mm, wired pin n to pin n. The plain 43025-1000 housing also fits (in stock at DigiKey, WM1787-ND), at the cost of the TPA's second lock. Every contact must be gold, because gold never mates tin. check_capbank_lead.py therefore checks the part number at both ends as well as the pins.

  • Ready-made leads are not suitable for the cab. Molex's 214755 female-to-female assemblies use 18 AWG UL 1061 wire, a style usually rated 80 °C, and their pin mapping is unverified.

Layout

Two rows of two cells lie flat, leads facing a centre strip, with J1 at the strip's foot and its mating face off the bottom edge. The string runs C1 (bottom left) up to C2, across to C3 and down to C4 (bottom right), so both of its ends land beside J1. The vents (the cells' closed ends) face the board's left and right edges.

text
    C2 ====]  TAP2  [==== C3
            TAP1 | TAP3
    C1 ====]   J1   [==== C4
  • Every inter-cell join is a pour on both layers.
  • VCAP and GND reach J1's front-row power pins round the row's ends and under the housing.
  • The taps and the NTC drop onto J1's back row from the strip.
  • The sense lines cross in the 1.5 mm channel between J1's rows: − sense on F.Cu, + sense on B.Cu. Each net tie sits in a pour keep-out and joins its cell pad through a trace of its own, so no stack current flows past a sense point. gen/layout.py's docstring has the details.

Assembly

  1. Bend the leads 90° at least 2 mm from the seal, over a ~2 mm radius, so the body lies flat with its end face ~4.5 mm from the holes. Don't pull or twist the leads at the seal; it can leak. Factory bent-lead versions exist (BCAP0025 P300 X12), but their bend geometry has not been checked against this footprint.
  2. Polarity: the longer lead is + on the Eaton and UCAP cells. Pad 1 is the square pad with the + beside it. A silk bar marks each body's − side.
  3. Bed each cell in neutral-cure silicone RTV. Acetoxy RTV gives off acetic acid, which corrodes the leads.
  4. Tie each column down. One miniature tie per slot pair, round both cells, two per column.
  5. Hand-solder only (~360 °C, under 5 s per lead), and don't wash the board. Keep the iron off the sleeves.
  6. Keep the vent ends clear of the enclosure wall.

Discharge the bank before unplugging it. Lower vshunt on CANary-PWR (bench button held, or I²C) until the red LED goes out. 6 F at 10 V across a screwdriver is a welding event.

Decisions and open items

  • The lead's pin map stays as it is (operator, 2026-10-20). Swapping pins 5 and 6 would uncross the sense lines here but create a crossing on CANary-PWR. Its + sense ballast (R20) sits beside J4 pin 5 and its − sense ballast (R16) beside pin 6, so PWR's sense routing is uncrossed today. The question would reopen only if PWR's J4 area had to be redone; the gold header is a footprint drop-in, so it doesn't.
  • Firmware: the GPI table needs the NTC's R–T curve (Vishay's online calculator, or Murata R44E for XH103).

Parts

132
QtyValueFootprintReferences
20100nF 50V X7RCapacitor_SMD:C_0603_1608MetricC2, C3, C4, C10, C17, C21, C23, C24, C28, C29, C32, C35, C36, C38, C41, C42 +4
9100k 1%Resistor_SMD:R_0603_1608MetricR1, R8, R10, R12, R22, R25, R27, R41, R47
610k 1%Resistor_SMD:R_0603_1608MetricR34, R35, R36, R37, R39, R42
6Fiducial_1mm_Mask2mmFiducial:Fiducial_1mm_Mask2mmFID1, FID2, FID3, FID4, FID5, FID6
51k 1%Resistor_SMD:R_0603_1608MetricR24, R32, R33, R38, R40
52.7R 1% 1WResistor_SMD:R_2512_6332MetricR16, R17, R18, R19, R20
5NTTFS5C673NLTAGPackage_SON:VSON-8_3.3x3.3mm_P0.65mm_NexFETQ2, Q3, Q4, Q5, Q7
4100k 1%Resistor_SMD:R_0402_1005MetricR43, R44, R45, R46
4MountingHole_2.7mm_M2.5MountingHole:MountingHole_2.7mm_M2.5MH1, MH2, MH3, MH4
310uF 50V X7RCapacitor_SMD:C_1210_3225MetricC20, C26, C27
31uF 25V X5RCapacitor_SMD:C_0603_1608MetricC5, C8, C22
34.7uF 25V X5RCapacitor_SMD:C_0805_2012MetricC9, C37, C40
347uF 50VCapacitor_SMD:CP_Elec_6.3x7.7C1, C18, C19
210nF 50V X7RCapacitor_SMD:C_0603_1608MetricC11, C13
222uF 25V X5RCapacitor_SMD:C_1206_3216MetricC15, C16
24.7k 1%Resistor_SMD:R_0603_1608MetricR30, R31
24.7uH Isat 14.4AInductor_SMD:L_Wuerth_XHMI-6060L1, L2
247uF 10V X5RCapacitor_SMD:C_1210_3225MetricC30, C31
28mOhm 1% 1WResistor_SMD:R_2512_6332MetricR14, R15
2BAT46WS-AQDiode_SMD:D_SOD-323FD5, D6
2BSS138Package_TO_SOT_SMD:SOT-23Q6, Q8
1100nF 25V X7RCapacitor_SMD:C_0603_1608MetricC33
110k 0.1%Resistor_SMD:R_0603_1608MetricR13
1120pF 50V C0GCapacitor_SMD:C_0603_1608MetricC12
1121R 1%Resistor_SMD:R_0603_1608MetricR6
1150k 1%Resistor_SMD:R_0603_1608MetricR4
11M 1%Resistor_SMD:R_0603_1608MetricR3
11N4148WDiode_SMD:D_SOD-123D4
11uF 50V X7RCapacitor_SMD:C_0805_2012MetricC39
1220nF 25V X7RCapacitor_SMD:C_0603_1608MetricC14
122pF 50V C0GCapacitor_SMD:C_0603_1608MetricC25
122uF 10V X5RCapacitor_SMD:C_1206_3216MetricC34
124.3k 1%Resistor_SMD:R_0603_1608MetricR23
127k 1%Resistor_SMD:R_0603_1608MetricR26
12x20 stacking hdr 13.5mm (DNP)Connector_PinSocket_2.54mm:PinSocket_2x20_P2.54mm_VerticalJ1
133.2k 1%Resistor_SMD:R_0603_1608MetricR21
15mOhm 1% 1WResistor_SMD:R_2512_6332MetricR28
1649k 1%Resistor_SMD:R_0603_1608MetricR9
1665k 1%Resistor_SMD:R_0603_1608MetricR11
171.5k 1%Resistor_SMD:R_0603_1608MetricR5
1732k 1%Resistor_SMD:R_0603_1608MetricR7
1BZT52C15Diode_SMD:D_SOD-123D1
1Cap bankConnector_Molex:Molex_Micro-Fit_3.0_43045-1000_2x05_P3.00mm_HorizontalJ4
1EVQ-P7A01PButton_Switch_SMD:SW_SPST_EVQP7ASW1
1GreenLED_SMD:LED_Kingbright_APA1606_1.6x0.6mm_HorizontalD7
1HAT outConnector_Molex:Molex_Micro-Fit_3.0_43045-0600_2x03_P3.00mm_HorizontalJ3
1INA226AIDGSRPackage_SO:TSSOP-10_3x3mm_P0.5mmU3
1LM61460AASQRJRRQ1canary-pwr:IC_LM61460AFSQRJRRQ1U2
1LM74700QDBVTQ1Package_TO_SOT_SMD:SOT-23-6U4
1LTC3350EUHF#PBFcanary-pwr:QFN-38_UHF_LITU1
1NUP2105LT1GPackage_TO_SOT_SMD:SOT-23D3
1PTC 0.5A 40Vcanary-pwr:Fuse_1812_Bourns_MF-MSMFF1
1RedLED_SMD:LED_Kingbright_APA1606_1.6x0.6mm_HorizontalD8
1SMBJ24ADiode_SMD:D_SMBD2
1STM32G031K8T6Package_QFP:LQFP-32_7x7mm_P0.8mmU5
1SUD50P06-15Package_TO_SOT_SMD:TO-252-2Q1
1SWDConnector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_HorizontalJ5
1TCA9511ADGKRcanary-pwr:SOIC8_DGK_TEXU8
1TCAN1043HDQ1Package_SO:SOIC-14_3.9x8.7mm_P1.27mmU7
1TPS7A1633QDGNRQ1canary-pwr:DGN0008C_TPS7A1633AQDGNRQ1_TEXU6
1Vehicle inConnector_Phoenix_MC:PhoenixContact_MC_1,5_4-G-3.81_1x04_P3.81mm_HorizontalJ2

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Questions

How big is the Canary pwr PCB?

It measures 65 × 56 mm and has 4 copper layers, 1.6 mm thick.

What parts does the Canary pwr use?

132 parts, built around the STM32G031K8T6, TCAN1043HDQ1, INA226AIDGSR and LM61460AASQRJRRQ1. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the Canary pwr KiCad files?

From the danbrunski/canary repository on GitHub, at the commit this page was made from: the board is hardware/canary-pwr-rev1.0/canary-pwr.kicad_pcb and its schematic hardware/canary-capbank-rev1.0/canary-capbank.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the Canary pwr design in my own project?

Its repository states no licence, so its author keeps all rights: ask danbrunski before reusing the design.