2 layers15 × 39 mm
2 layers49 × 39 mm
Pole panellised
cillian64/thegrid2The·Grid - Interactive polychromatic lighting array
- Size
- 49 × 39 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 100
- Nets
- 18
- Pads
- 440
- Tracks, vias
- 1,028, 116
- Pours
- 4
- Routed
- Yes
- KiCad
- KiCad 4
- Created
- 7 Jun 2014
- Updated
- 16 Mar 2017
Overview
Pole panellised is an open-source printed circuit board by cillian64, from the cillian64/thegrid repository on GitHub. It is a 2-layer board of 49 × 39 mm with 100 parts on 18 nets, routed with 1,028 tracks and 116 vias.
It is built around the LD1117S33TR(MS) and LMX93. Its parts include 32 capacitors, 20 connectors, 16 transistors, 12 resistors and 12 ICs. It belongs with the STM32 boards of this library.
Main components
2README
README.mdThe·Grid
The·Grid is an installation at EMF 2014 and 2016. This repository contains the hardware, firmware, software, and miscellaneous documentation and scripts that go with it.
Hardware
All the PCB designs live in the hardware/ folder. They're done in KiCAD.
Firmware
The firmware that runs on the pole PCBs (new in 2016), which controls the RGB
LED and buzzer and reads data from the serial bus, lives in firmware/polefw.
The firmware that runs on the driver PCB, which is basically a glorified USB to
RS422 serial widget, lives in firmware/driverfw.
Both use ChibiOS (16.1) so you should git submodule update --init to get that
checked out. Additionally you'll want to patch a bug in ChibiOS, see the README
in firmware/ for more details.
Software
The software runs code-defined patterns of light and sound on The·Grid itself. It's written in Python 3, using asyncio, with some WebGL for an in-browser simulation.
It's fairly easy to add your own patterns, please see the README in software/
for more details.
Parts
100| Qty | Value | Footprint | References |
|---|---|---|---|
| 16 | 100n | agg:0603 | C1, C1, C1, C1, C3, C3, C3, C3, C5, C5, C5, C5, C6, C6, C6, C6 |
| 16 | MTM232270LBF | agg:SOT-323 | Q1, Q1, Q1, Q1, Q2, Q2, Q2, Q2, Q3, Q3, Q3, Q3, Q4, Q4, Q4, Q4 |
| 8 | 10k | agg:0603 | R1, R1, R1, R1, R2, R2, R2, R2 |
| 4 | 10n | agg:0603 | C4, C4, C4, C4 |
| 4 | 10u | agg:0603 | C7, C7, C7, C7 |
| 4 | 1M | agg:0603 | R3, R3, R3, R3 |
| 4 | 1u | agg:0603 | C8, C8, C8, C8 |
| 4 | 4u7 | agg:0603 | C2, C2, C2, C2 |
| 4 | BUS_IN | agg:S02B-PASK-2 | P2, P2, P2, P2 |
| 4 | BUS_OUT | agg:S02B-PASK-2 | P3, P3, P3, P3 |
| 4 | LD1117S33TR | thegrid:TO-252-3 | U1, U1, U1, U1 |
| 4 | LEDs | Pin_Headers:Pin_Header_Straight_1x04 | P5, P5, P5, P5 |
| 4 | LMx93 | SOIC-8 | IC1, IC1, IC1, IC1 |
| 4 | POWER_IN | thegrid:minipow_edge | P1, P1, P1, P1 |
| 4 | RST | agg:TESTPAD | TP1, TP1, TP1, TP1 |
| 4 | SPEAKER | thegrid:piezo | SP1, SP1, SP1, SP1 |
| 4 | STM32F0xxKxUx | agg:QFN-32-EP-ST | IC2, IC2, IC2, IC2 |
| 4 | SWD_TC | agg:TC2030-NL | P4, P4, P4, P4 |
Questions
How big is the Pole panellised PCB?
It measures 49 × 39 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Pole panellised use?
100 parts, built around the LD1117S33TR(MS) and LMX93. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Pole panellised KiCad files?
From the cillian64/thegrid repository on GitHub, at the commit this page was made from: the board is hardware/pole/pole_panellised.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Can I use the Pole panellised design in my own project?
Its repository states no licence, so its author keeps all rights: ask cillian64 before reusing the design.
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