
OpenDTU
plewka/ESP-Solar_OpenDTU
PCB for OpenDTU in Cable Branchbox, LineSupply w. Fuses, RS485/RS232-Olimex, Relais, DS2485 OneWire, I2C-Header...

Open-source, digitally controlled high-voltage AC power supply for cold atmospheric plasma (CAP) research, developed with a specific focus on flexible-endoscope decontamination applications.
HVGene is an open-source printed circuit board by Teille98, from the Teille98/HVGene-OpenHardware repository on GitHub. It is a 2-layer board of 94.8 × 57.5 mm with 33 parts on 32 nets, routed with 149 tracks and 1 via.
It is built around the MCP1416-E/OT, LM2574-5.0YN and IRFI4321PBF, with the US1J and SB160 among its other parts. Its parts include 9 capacitors, 9 connectors, 4 resistors, 4 ICs and 3 diodes. It belongs with the SAM D and SAM boards of this library.
Open-source, digitally controlled high-voltage AC power supply for cold atmospheric plasma (CAP) research, developed with a specific focus on flexible-endoscope decontamination applications. The platform delivers either continuous sinusoidal high-voltage excitation or pulsed AC trains, with explicit user control over input voltage, operating frequency, duty cycle, timing, and operating mode.
This repository accompanies the following HardwareX article:
Open-Source High Voltage Power Supply for Cold Atmospheric Plasma Generation, HardwareX (2026). DOI: to be added once assigned.
Archived on Zenodo: 10.5281/zenodo.21889908.
If you use this hardware, firmware, or documentation, please cite the article above.
This project mixes three kinds of content, each released under the license most
appropriate for that kind of content — see the LICENSE file inside each folder
for the exact terms.
HVGene_OpenHardware/
├── hardware/ Electronics and mechanical design files
│ ├── LICENSE CERN-OHL-P-2.0 (permissive open hardware licence, unmodified)
│ ├── NOTICE Copyright notice (kept separate — the licence text itself
│ │ must not be modified, per its own Preamble)
│ ├── KiCAD/ PCB schematic and layout (push-pull inverter board);
│ │ Article_Figure3_version/ = schematic as drawn in Figure 3
│ │ of the article
│ ├── CAD-Fusion360/ 3D mechanical design (enclosure, mounting)
│ ├── Cutting/ Laser-cutting SVG files (LV/HV plates)
│ └── BOM.xlsx Bill of materials
├── firmware/ RP2040 / MicroPython control firmware
│ ├── LICENSE MIT
│ ├── main.py, lib/ Firmware source
│ └── tests/ Bench validation scripts (I2C, PIO, timing)
├── docs/ Build photos, diagrams, and other documentation media
│ ├── LICENSE CC BY-SA 4.0
│ └── Figures/ Article_Figures/ = the article figures (Fig01–Fig29) and
│ Supplementary Material figures (FigS1–FigS6); plus
│ device/setup/plasma photos, CAD renders, diagrams (with
│ their draw.io/TikZ sources), build-step and scope images
└── data/ Validation dataset (all measured operating points, raw and
derived quantities) behind the article's validation sectionThe folders above are the design files listed in the article's Design files summary (Table 3).
The version tagged and archived alongside the HardwareX article submission is the exact hardware/firmware state described and validated in that article. This repository may continue to evolve after that point (bug fixes, improvements, community contributions); the archived release is the one to use for reproducing the results reported in the article.
This hardware generates high voltages (up to several tens of kV) and involves mains-connected power electronics. Building and operating it requires appropriate electrical safety training. See the "Safety Concerns" and "Operation instructions" sections of the article before use.
| Qty | Value | Footprint | References |
|---|---|---|---|
| 2 | 0.01uF | Capacitor_THT:C_Rect_L7.0mm_W3.5mm_P5.00mm | C1, C2 |
| 2 | 0.1uF | Capacitor_THT:C_Rect_L7.0mm_W3.5mm_P5.00mm | C3, C5 |
| 2 | 100 k | Resistor_THT:R_Axial_DIN0516_L15.5mm_D5.0mm_P5.08mm_Vertical | R1, R2 |
| 2 | 1uF | Capacitor_THT:C_Rect_L7.0mm_W4.5mm_P5.00mm | C4, C6 |
| 2 | 47 kΩ | Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical | R4, R5 |
| 2 | Conn_01x03_Socket | Connector_JST:JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical | J8, J9 |
| 2 | Conn_01x06 | Connector_JST:JST_XH_B6B-XH-A_1x06_P2.50mm_Vertical | J4, J6 |
| 2 | IRFI4321PBF | IRFI4321:TO254P483X1018X2095-3P | Q1, Q2 |
| 2 | MCP1416 | Package_TO_SOT_SMD:SOT-23-5 | U2, U3 |
| 2 | Screw_Terminal_01x02 | Connector_Phoenix_MSTB:PhoenixContact_MSTBA_2,5_2-G-5,08_1x02_P5.08mm_Horizontal | J1, J2 |
| 2 | US1J | Diode_THT:D_DO-41_SOD81_P2.54mm_Vertical_AnodeUp | D1, D2 |
| 1 | 10µF | Capacitor_THT:C_Rect_L7.0mm_W4.5mm_P5.00mm | C7 |
| 1 | 22 uF | capa 22uF:CAPPRD200W52D500H1250 | C8 |
| 1 | 220 uF | capa 220uF:CAPPRD500W60D1000H1350 | C9 |
| 1 | 330 uH | inductance 330uH:WE-TIS_111190 | L1 |
| 1 | Conn_01x02_Socket | Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical | J7 |
| 1 | Conn_01x04 | Connector_JST:JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical | J5 |
| 1 | Jumper_2_Open | Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical | JP1 |
| 1 | LM2574-5.0YN | LM2574:DIP762W57P254L952H343Q8N | IC1 |
| 1 | SB160 | SB160:DIOAD1405W86L465D235 | D3 |
| 1 | Screw_Terminal_01x03 | Connector_Phoenix_MSTB:PhoenixContact_MSTBA_2,5_3-G-5,08_1x03_P5.08mm_Horizontal | J3 |
| 1 | SeeeduinoXIAO | FabInventory:SeeedStudio_XIAO_RP2040 | U1 |

plewka/ESP-Solar_OpenDTU
PCB for OpenDTU in Cable Branchbox, LineSupply w. Fuses, RS485/RS232-Olimex, Relais, DS2485 OneWire, I2C-Header...

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It measures 94.8 × 57.5 mm and has 2 copper layers, 1.6 mm thick.
33 parts, built around the MCP1416-E/OT, LM2574-5.0YN, IRFI4321PBF and US1J. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
From the Teille98/HVGene-OpenHardware repository on GitHub, at the commit this page was made from: the board is hardware/KiCAD/HVGene.kicad_pcb and its schematic hardware/KiCAD/Article_Figure3_version/HVGene.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Its repository states no licence, so its author keeps all rights: ask Teille98 before reusing the design.