SkyRizz ESPSOL

ESPSOL DevKit

An open-hardware, coin-sized ESP32-S3 development board with an on-board secure element, 6-axis IMU, PDM microphone, buzzer, USB-C, and Li-Po charging — all on a 40.6 mm (1.6") round, 2-layer PCB.

Built for the Solana ecosystem: the tamper-resistant secure element, user buttons, and wireless connectivity make it a ready platform for hardware wallets, HID signers, Solana Pay terminals, and DePIN devices. See Built for the Solana ecosystem.

Developed by SkyRizz. Licensed under the CERN Open Hardware Licence v2 – Strongly Reciprocal (see LICENSE.md).

Top (front)	Bottom (back)

Overview

The ESPSOL DevKit is built around the ESP32-S3-WROOM-1-N16R8 module. It exposes 12 GPIO on two 8-pin 2.54 mm through-hole headers and integrates the peripherals needed for connected, secure, audio-capable applications without external wiring.

Pinout

Two 8-pin headers break out power and 12 GPIO. Pin 1 is the square pad on each header. Silkscreen labels are shown on the bottom side of the board.

J4 — left header

J3 — right header

Power note: VCC/VSYS follows the battery/USB input voltage and is not regulated. Use the 3V3 pin for logic-level supply.

On-board peripheral connections (fixed)

These GPIO are dedicated to on-board devices and are not available on the headers.

GPIO35–37 are used internally by the octal PSRAM and are unavailable. GPIO8, GPIO14, GPIO45, and GPIO46 exist on the module but are not routed to the headers on this revision.

Buttons & LEDs

Two indicator LEDs — LD1 (red) and LD2 (blue) — are driven by the charger's STAT output and show battery charge status (charging / charge complete). They are not connected to a GPIO.

USB — HID / UART switcher

The USB-C connector (J2) is routed to one of two targets through an FSUSB42 2:1 USB switch (U8). GPIO13 selects which endpoint owns the data lines:

• Native USB (HID) — the ESP32-S3 built-in USB PHY (D+/D− on GPIO19/GPIO20, via series resistors R29/R30). Enumerates as USB-Serial-JTAG for flashing and debugging, or as a USB HID device (keyboard/mouse/etc.) and other native device classes.
• CH340C USB-UART — a classic serial bridge to UART0 (GPIO43/44), for legacy serial flashing and monitoring.

                                   ┌─ Port 1 (HSD1) ─ R29/R30 ─ ESP32-S3 native USB (HID / JTAG)
USB-C (J2) ─ SRV05-4 ESD ─ FSUSB42 ┤
                              ▲    └─ Port 2 (HSD2) ───────────── CH340C  ─ UART0 (GPIO43/44)
                              │
                          SEL = GPIO13

USB data lines are protected by an SRV05-4 TVS/ESD array (D2).

Power

VSYS is available on J4 pin 2 and regulated 3V3 on J3 pin 2. The system/battery rail can be read on GPIO3 (ADC1) through a 22 k/22 k divider — actual voltage ≈ ADC_reading × 2.

Using the on-board modules

All fixed peripherals hang off the pins below. Examples use the Arduino-ESP32 / ESP-IDF pin names; adapt to your framework.

I²C bus (IMU + Secure Element)

Both the IMU and the secure element share one I²C bus:

Wire.begin(/*SDA=*/10, /*SCL=*/9);   // GPIO10 = SDA, GPIO9 = SCL

LSM6DS3 IMU (accelerometer + gyroscope)

• Bus: I²C at 0x6A (GPIO9/10).
• Data-ready / motion interrupt: GPIO4 (INT1). Configure it as an input and attach an ISR for wake-on-motion / tap / free-fall events.
• Use ST's LSM6DS3 driver or any generic library; poll or drive from the GPIO4 interrupt.

SE050 secure element

• Bus: I²C at 0x48 (GPIO9/10).
• Reset line: GPIO5 — drive low then high to reset the chip on power-up.
• Tamper-resistant storage for private keys, credentials, and crypto operations. Use NXP's Plug & Trust middleware (or a lightweight I²C driver) to provision and use keys without exposing them to the ESP32.

PDM microphone (SPH0641LM4H-1)

• Clock: GPIO12, Data: GPIO11.
• Drive with the ESP32-S3 I²S peripheral in PDM-RX mode (i2s_pdm_rx).
• Provide a clock in the 1–3.5 MHz range; the mic streams 1-bit PDM that I²S decimates to PCM.

Buzzer (KSSG33J12-3)

• Signal: GPIO48 → SS8050 transistor driver (Q4) → buzzer, powered from VSYS.
• Active high. For tones, drive GPIO48 with a PWM / LEDC channel:

ledcAttach(48, 2700 /*Hz*/, 8);   // ~2.7 kHz is near the buzzer's resonance
ledcWrite(48, 128);               // 50% duty = beep;  0 = silent

Battery / power monitoring

• GPIO3 (ADC1) reads VSYS through a 22 k/22 k divider → multiply the reading by 2 for the real rail voltage.
• Charge status is shown by the on-board LEDs (LD1 red / LD2 blue), driven by the MCP73831 STAT pin — no GPIO needed.

Buttons

Each button connects its GPIO to GND, so enable the internal pull-up and read active-low:

pinMode(47, INPUT_PULLUP);   // SW1
pinMode(21, INPUT_PULLUP);   // SW2
pinMode(1,  INPUT_PULLUP);   // SW3

USB HID / UART switcher

Set GPIO13 to choose what the USB-C port presents (see USB — HID / UART switcher):

pinMode(13, OUTPUT);
digitalWrite(13, LOW);    // one setting → ESP32-S3 native USB (HID / USB-JTAG)
digitalWrite(13, HIGH);   // other setting → CH340C USB-UART bridge

The two states map to Port 1 (native USB) and Port 2 (CH340). Confirm the polarity on first bring-up and lock it into your firmware default.

Built for the Solana ecosystem

The ESPSOL DevKit pairs a wireless MCU with a tamper-resistant secure element, user-confirmation buttons, and audio feedback — the exact ingredients for self-custody and on-chain device applications. The round form factor is designed to drop into wearables, fobs, and point-of-sale enclosures.

Example use cases:

• Hardware wallet / cold signer — keep private keys inside the SE050, confirm transactions with SW1–SW3, and beep on approval. The ESP32-S3 talks to a companion app over BLE or Wi-Fi while keys never leave the secure element.
• USB HID hardware authenticator — flip the HID/UART switcher (GPIO13) to native USB and enumerate as a HID device that signs transactions or acts as a 2FA/security key for a Solana wallet on a host computer.
• Solana Pay terminal — a compact Wi-Fi point-of-sale that generates Solana Pay requests; add a display/reader on the J3/J4 headers and use the buzzer for payment-confirmation tones.
• DePIN / IoT node — report sensor and motion data (LSM6DS3) or audio (PDM mic) to a Solana program, with the SE050 providing a hardware device identity for signed attestations.
• Voice-triggered wallet / assistant — capture wake words or commands through the PDM microphone and trigger on-chain actions.
• Wearable badge / tap-to-pay fob — battery-powered, round, and pocketable, with charge-status LEDs and Li-Po management already on board.

The hardware provides the secure key custody, connectivity, and I/O; the Solana integration (RPC, transaction building, signing flow) lives in your firmware and companion app.

Bill of materials

Interactive BOM: hardware/bom/ibom.html

Repository layout

hardware/                    KiCad project
  SkyRizzESPSOL.kicad_pro    Project
  SkyRizzESPSOL.kicad_sch    Schematic
  SkyRizzESPSOL.kicad_pcb    PCB layout
  bom/ibom.html              Interactive BOM
assets/                      Board renders
LICENSE.md                   CERN-OHL-S v2

License

Hardware design files are released under the CERN Open Hardware Licence Version 2 – Strongly Reciprocal (CERN-OHL-S v2). See LICENSE.md.