ESP Smart IoT Power Bank

Smart IoT Power Bank — Hardware (PD Edition)

A bidirectional USB-C Power Delivery (PD) power bank built around a software-defined PD stack and an I²C buck-boost charger. This repository holds the KiCad hardware design (schematic, layout, BOM, fabrication outputs). The firmware lives in a separate repository.

Firmware: smart-iot-power-bank-firmware

Smart IoT Power Bank

1. Overview

The board implements a professional power-management architecture comparable to those found in modern laptops. The same USB-C port handles input (sink) and output (source/OTG), limited to a robust 30 W. Energetic characterization (V/I telemetry, efficiency) is done entirely with the internal 16-bit ADCs of the charge controller, avoiding external sense amplifiers.

2. Hardware Architecture

A. Power Path & USB-C Communication

B. Protection (TVS / ESD / Clamps)

C. Sensing & Intelligence (IoT layer)

D. Connectors, Switches, Indicators

Full part list with manufacturer numbers, footprints and datasheets: ESP_Smart_IoT_Power_Bank.csv.

3. Engineering Features & Physics

I. Cascaded Power Supply (Logic Isolation)

To avoid system reboots under heavy load, the supply is cascaded:

1. Primary stage — the BQ25792 generates the system rail V_SYS from the 4S pack.
2. Secondary stage — a dedicated TPS54202 bucks V_SYS down to a constant 3.3 V for the logic. The ESP32 therefore always sees a clean rail, independent of current spikes in the power stage.

II. Efficient 4S Power Routing (Buck & OTG)

The 4S pack (14.8 V) minimizes conversion losses:

• Buck mode (sink): at 20 V input the IC acts as an efficient step-down.
• Buck/boost mode (source): in OTG, 5 V / 9 V / 12 V are produced highly efficiently by buck conversion; only 20 V profiles (e.g. laptops) require a slight boost.

III. Thermal & Electrical Derating

Thanks to the 4S configuration, PCB currents stay below 3 A even at 30 W:

I_bat_max = P_out / (U_bat · η)
I_bat_max = 30 W / (12.0 V · 0.9) ≈ 2.7 A   (worst case, empty pack)

On overheat (NTC > 60 °C) the ESP32 throttles PD power via software re-negotiation down to 5 W (5 V / 1 A) as a fallback.

4. PCB Stackup & Layout

4-layer board, built to Aisler's stackup and design rules.

The dual inner ground planes give the high-speed pairs a continuous reference and a low-impedance return for the power stage.

Differential pairs

Two impedance-controlled 90 Ω differential pairs (USB 2.0 spec):

1. USB power port (BQ25792): backwards-compatible USB data for the power path.
2. Debug/flash port (ESP32-C3): USB used to flash and debug the MCU.

Both pairs are protected by the low-capacitance TPD4E05U06 ESD arrays so the added capacitance does not degrade signal integrity.

Layout guidelines

• Ground partitioning — clean ground concept separating the power stage (BQ25792) from the logic (ESP32 / TPS54202).
• Copper polygons — power paths (V_BUS, V_BAT, V_SYS) routed as filled polygons.
• Thermal management — implemented high power rails on both sides of the board to increase thermal capacity and placing a generous amount of vias to distribute current evenly

5. Design Decisions Log

• Dual-MOSFET reverse-polarity protection (Q1/Q2, CSD17581Q3A) instead of a single series diode — near-zero conduction loss on the power path.
• VBUS TVS (TVS2200) for surge clamping on the high-current bus.
• Low-capacitance TVS/ESD (TPD4E05U06) on CC lines and the differential pairs to preserve signal integrity.
• Two 90 Ω impedance-controlled diff pairs: one for backwards-compatible USB power data (BQ), one dedicated to flashing/debugging the MCU.
• Aisler chosen as fab house — the stackup and design rules in this project are tuned to Aisler's process.

6. Status

Hardware design in KiCad. See the firmware repository for the FreeRTOS PD stack.