EPS mppt board

CubeSat 4-Channel Distributed MPPT & Electrical Power System (EPS)

A flight-ready 4-channel distributed Maximum Power Point Tracking (MPPT) battery charging and power distribution board designed in KiCad for CubeSat nanosatellite missions. Engineered for the Queen's Space Engineering Team (QSET) satellite branch.

Key Features

• 4x Distributed Synchronous MPPT Buck Chargers (LTC4162):
  • 4 independent MPPT tracking channels (1 per CubeSat body face), eliminating partial shading and thermal mismatch losses across orbit.
  • Autonomous Constant-Current / Constant-Voltage (CC/CV) power-path management charging a 2S Li-ion battery bus (~8.4V nominal).
  • Phase-synchronized 1.5 MHz switching frequency via MCU clock distribution buffer to prevent harmonic beat frequencies and reduce EMI.
• Microcontroller & Rad-Tolerant Storage Core:
  • STM32L496 ARM Cortex-M4: Ultra-low-power MCU handling housekeeping telemetry, fault recovery, and bus communications.
  • 4 MB Radiation-Hardened MRAM: Immune to Single-Event Upsets (SEU) and Total Ionizing Dose (TID), preserving black-box flight telemetry across power resets.
  • 4-Pin High-Vibration Crystal Oscillator: Superior mechanical stability against rocket launch vibrational loads compared to traditional 2-pin crystals.
  • Deterministic Hardware Watchdog (TPS3823A): Hardware supervisor with active-low reset and Schottky diode isolation protecting against SEU lockups in LEO.
• Satellite Bus Communications & Auxiliary Power Path:
  • Dual Redundant CAN Bus Transceivers: Conforms to European CubeSat standard bus communication architecture.
  • I2C Bus Multiplexer (TI TCA9548A): 8-channel I2C switch addressing 4 identical LTC4162 chargers at fixed I2C addresses.
  • Dual Synchronous Buck Converter (LTC3633): Monolithic dual synchronous buck generating regulated +3.3V and +5.0V system rails (<15 mV ripple).
  • Autonomous Power-Path & Cold-Start (LTC4412): Ideal diode controller providing seamless fallback between battery and direct solar harvest for dead-battery bootstrapping.
• Power Telemetry & Comprehensive eFuse Protection:
  • INA3221 Triple-Channel Current/Voltage Monitor: Digital I2C telemetry reporting bus voltages, currents, and power consumption.
  • TPS25947 Precision eFuses: Dedicated protection on output rails with programmable current limits (1.33 A clamp on +3.3V), slew rate inrush control (5 V/ms), transient blanking (0.44 ms), hardware UVLO/OVLO windowing (3.02 V – 3.63 V), and remote MCU/OBC shutdown.
• Form Factor & Mechanical Integrity:
  • Standard PC/104 CubeSat stackable form factor.
  • Dedicated battery interface with 4-wire Kelvin sensing and NTC thermistor inputs.
  • 6-Layer stackup with solid ground reference planes, top-side RF/switching hot loops, and vibration-resistant soft-termination MLCC capacitors.

System Architecture & PCB Renders

Full Board 3D Model

Top & Bottom Layout Renders

Top Layer (Switching & Hot Loops)	Bottom Layer (Routing & Ground Shield)

Top-Level Hierarchical Schematic

Technical Specifications

Power Telemetry & eFuse Configuration

Each regulated rail is protected by a TI TPS25947 eFuse and monitored by a TI INA3221 current/voltage telemetry IC:

• Current Limit Threshold ($I_{\text{LIM}}$): $$I_{\text{LIM}} = \frac{13.33}{R_{\text{ILIM}}\ [\text{k}\Omega]} = \frac{13.33}{10\text{ k}\Omega} = 1.33\text{ A}$$
• Output Slew Rate & Inrush Control ($\frac{dV}{dt}$): $$\frac{dV}{dt} = \frac{500}{C_{dV/dt}\ [\text{pF}]} = \frac{500}{100\text{ pF}} = 5\text{ V/ms}$$
• Overcurrent Fault Blanking Timer ($t_{\text{ITIMER}}$): $$t_{\text{ITIMER}} = C_{\text{ITIMER}}\ [\text{nF}] \times 0.2 = 2.2\text{ nF} \times 0.2 = 0.44\text{ ms}$$
• Voltage Window (UVLO / OVLO): $$\text{Operational Window: } 3.02\text{ V} \le V_{\text{IN}} \le 3.63\text{ V}$$

Hierarchical Schematic Structure

The hardware schematic is split into modular hierarchical sheets:

Repository Structure

Sat_MPPT_PCB/
├── .gitignore                      # Standard KiCad ignore rules
├── README.md                       # Board documentation and specifications
│
├── docs/                           # Documentation & exports
│   ├── bom/
│   │   └── EPS_mppt_board.csv      # Complete Bill of Materials
│   ├── pdf/
│   │   └── EPS_mppt_board.pdf      # Complete schematic PDF
│   └── svg/                        # Exported vector schematics per sheet
│       ├── EPS_mppt_board.svg
│       ├── EPS_mppt_board-3.3V Logic.svg
│       ├── EPS_mppt_board-MPPT IC.svg
│       └── ...
│
├── scripts/                        # Simulation & analysis tools
│   └── mppt_efficiency_sim.py      # 4-MPPT vs 1-MPPT orbital comparison simulation
│
├── archive/                        # Early design prototypes and iterations
│   └── prototypes/
│
├── 3D_Models/                      # 3D STEP/STP component models
│
├── sym-lib-table                   # KiCad Symbol Library Table

Simulation & Verification

• Switching & Transient Simulations: LTspice models verified buck converter stability, hot-loop parasitic response, and transient load step response (0.1A to 3.0A step with <15 mV voltage deviation).

• SPICE: All IC's with available SPICE models were simullated in PSPICE or LTSPICE.

Project Background

• Detailed Technical Writeup: Read the full post on Creating an MPPT System for Max Charge Efficiency on Satellite