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6 layers84 × 98 mmFujiNet-5200-Rev0, the printed circuit board in 3D

Schematics and design files for FujiNet hardware

Size
84 × 98 mm
Copper layers
6
Thickness
1.6 mm
Parts
145
Nets
178
Pads
601
Tracks, vias
1,192, 594
Pours
33
Routed
Yes
KiCad
KiCad 10.0 (file 20260206)
Created
10 May 2020
Updated
6 Nov 2026

Overview

FujiNet-5200-Rev0 is an open-source printed circuit board by FujiNetWIFI, from the FujiNetWIFI/fujinet-hardware repository on GitHub. It is a 6-layer board of 84 × 98 mm with 145 parts on 178 nets, routed with 1,192 tracks and 594 vias.

It is built around the RP2354B, SN74HCT541PWRE4 and 74LVC1G17GW,125-JSM, with the ESP32-S3-WROOM-1-N16R8, AP63203WU and AP63205WU among its other parts. Its parts include 52 capacitors, 30 resistors, 11 ICs, 9 diodes and 4 connectors. It belongs with the ESP32 and RP2350 boards of this library.

Main components

12

README

ATARI-2600/Fujiversal-Atari2600-Rev1/README.md

Fujiversal-Atari2600 Rev1

All-in-one Atari 2600 FujiNet cartridge, the RP2354A successor to the RP2040 Rev0 (branch atari2600-rev0). It is the hardware for the 2600 bring-up in fujinet-firmware (branch 2600-experiment, worktree ~/Workspace/fn-2600).

  • RP2354A (RP2350A + 2 MB flash in one QFN-60) runs the cart firmware (pico/atari-2600, board fujivcs, ported to the RP2350 as listed below). The cartridge port goes straight to the RP: A0-A12 on GP2-GP14 and D0-D7 on GP15-GP22, exactly as include/vcs_pins.h. RP2350 GPIO0-25 are "Digital IO (FT)": 5.5 V-tolerant while IOVDD is 3.3 V, and a 3.3 V high clears the 6507's TTL VIH (2.0 V). No '245 buffers and no direction pin: the firmware's per-access output enable is the only direction control.
  • ESP32-S3-WROOM-1-N16R8 runs the fujiversal-atari2600 build of fujinet-firmware and is the RP's USB host (S3 IO19/IO20 -> 27R -> RP USB; the RP enumerates as CDC, VID 0xCafe). There is no UART between the chips.
  • USB-C: power + CP2102N UART with UMH3N auto-program (flashes the S3).
  • microSD (push-push, SPI on IO38-41, card-detect IO42), on the right edge.
  • WS2812B-2020 status LED (IO48, on +5V) and a red RP activity LED (GP25).
  • Buttons: RESET (resets both chips: the way back to the browser), BOOTSEL (RP), S3 EN, S3 BOOT. The S3 can also force the RP into reset or BOOTSEL itself (IO4 -> RUN, IO5 -> QSPI_SS, active low through 1k).
  • Console 5 V sense on GP27 (100k/150k, 3.0 V at 5 V): the firmware can tell a powered console from a USB-only cart.

4 layers, fully routed, DRC clean with schematic parity, JLCPCB fab + assembly files in exports/jlcpcb/. Everything is generated from tools/design.py (circuit), tools/sch_layout.py (schematic drawing) and tools/placement.py (layout): edit those, never the KiCad files.

Pin contract

RP2354AQFN-60 pinNetFirmware
GP2-GP144,5,7-10,12-18A0-A12 (CA0-CA12)ADDR_PIN 2, ADDR_BITS 13
GP15-GP2219, 27-29, 31-34D0-D7 (CD0-CD7)D0_PIN 15
GP2537RP_LED (680R, red LED)PICO_DEFAULT_LED_PIN
GP2741VSENSE (console 5 V x 0.6)new: power sense
GP0 / GP12 / 3RP_TX / RP_RX (TP4 / TP5)debug UART
GP2640not connectedthe RP2040 board's DIR_PIN (harmless if written)
GP23, 24, 28, 29not connected
USB DP/DM52 / 5127R -> S3 IO20 / IO19CDC device
RUN / QSPI_SS26 / 6010k pull-ups; 1k from S3 IO4 / IO5; RESET / BOOTSEL buttonsPIN_RP2040_RUN 4, PIN_RP2040_BOOTSEL 5
SWCLK / SWDIO24 / 25TP1 / TP2 (TP3 GND)first flash

ESP32-S3 pins are exactly include/pinmap/fujiversal-atari2600.h: SD CS 41, SCK 39, MISO 40, MOSI 38, CD 42 (10k pull-up), LED strip 48, UART0 43/44, RUN 4, BOOTSEL 5, USB host 19/20. tools/check_nets.py checks all of this against the firmware headers (290 checks).

Edge connector

2x12 gold fingers at 2.54 mm pitch, 1.5 x 7.0 mm, starting 0.5 mm from the edge; tab 32.4 mm with 45-degree shoulders (geometry and orientation from the FujiPlusCart prototype gerbers, ../FujiPlusCart-Prototype).

FaceFingers, left -> right (component face toward you)
F.Cu (components, console rear)13 D3, 14 D4, 15 D5, 16 D6, 17 D7, 18 A12, 19 A10, 20 A11, 21 A9, 22 A8, 23 +5V, 24 GND
B.Cu (label side, console front)12 GND, 11 D2, 10 D1, 9 D0, 8 A0, 7 A1, 6 A2, 5 A3, 4 A4, 3 A5, 2 A6, 1 A7 (pin 1 behind pin 24)

The port carries no R/W, clock, chip select or reset: A12 is the only decode.

Schematic

Root + four wired sheets, drawn left to right in signal-flow order (docs/Fujiversal-Atari2600-Rev1-schematic.pdf):

  1. edge-rp2354a: the edge connector on the left, the RP2354A beside it (mirrored so its GPIO column faces the edge): A0-A12 and D0-D7 are 21 straight wires from finger to pin. Supplies and Raspberry Pi's core regulator across the top; clock, RUN/BOOTSEL, USB and SWD leave on the right.
  2. esp32s3-sd: EN/BOOT in on the left; UART, USB, SD and LED out on the right.
  3. usb-uart: USB-C -> ESD -> CP2102N -> UART + auto-program.
  4. power: console 5 V (and its sense divider) and VBUS -> +5V -> buck and RP LDO.

Nets cross sheets only on global labels at the page edges; every pin is wired or flagged no-connect. gen_sch.py lints each sheet (connectivity, overlaps) and checks the written schematic's netlist (kicad-cli) against design.py net by net.

Power

  • Console 5 V (finger 23) through an AO3401A P-FET (gate = VBUS): fully on without USB; with USB in, the gate is at VBUS and only the body diode is left, so USB never back-feeds the console. R19 (4.7k) holds the gate down against the SS34's reverse leakage. USB VBUS through an SS34. Both meet on +5V.
  • +3V3 (AP63203 buck, 2 A): ESP32-S3, microSD, CP2102N.
  • +3V3_RP (AP2112K LDO, 20 us start-up, ~16-40 mA): every RP2354A supply pin, including the core regulator's VREG_VIN and VREG_AVDD (through 33R), which the datasheet asks to rise together. The pads are 5 V-tolerant only while IOVDD is powered; the LDO rises with the console rail, the buck's soft-start would not.
  • DVDD 1.1 V from the RP's own regulator (3.3 uH AOTA, Raspberry Pi's minimal-design corner layout).
  • Budget (estimate): ~60 mA idle and ~350 mA during WiFi TX on +3V3, about 250-300 mA peak from the console's 7805. Measure on a 2600 Jr before relying on console-only power.

Layout

  • Board: 54.4 x 88 mm, 1.6 mm, Rev0's outline (same shell). Parts only above y 90.5 (the shell bottom, 25.5 mm above the contact edge).
  • Stack (4 layers): F.Cu signals + GND pour / In1 GND plane / In2 +3V3 plane with a +3V3_RP island under the RP and its decoupling and a DVDD island (+ lobe) under its core / B.Cu signals + GND pour. Inner planes stop 9 mm from the insertion edge; the finger strip is a rule area (fingers only).
  • Placement: the RP2354A at rotation 90, so A0-A9 sit on its south side in the order of the B.Cu address fingers below it; the data lines (D1-D7 at its north-east corner) run north-about and down the west corridor to the data fingers, so the two buses never cross. The core-regulator corner is Raspberry Pi's own RP2350A minimal-design layout (MIT), grafted at the RP and turned with it. The ESP32-S3 sits top-left with its antenna flush with the top edge over a band that is copper-free on every layer; microSD on the right edge, USB-C on the top edge (its shell face 0.45 mm past the edge, HRO's recommended PCB-edge position), power at the bottom right, buttons on the left edge.
  • Rules: 0.2 mm / 0.15 mm default (0.5 mm power, 0.3 mm VBUS, 0.25 mm USB), 0.6/0.3 mm vias (0.5/0.25 under the RP), 0.25 mm copper-to-edge, 0.125 mm annular, 0.12 mm clearance floor for the neck-downs at 0.4 mm pitch. JLCPCB multilayer minimums: 0.09 mm track/space, 0.25/0.15 mm via.
  • Shell: case/ (see case/case-spec.md), two options, both driven by case/board-anchors.scad (generated from the placement): a clamshell over the board's top with the tab bare (Fujiversal-Atari2600-Shell.scad), or a full-size cartridge re-modelled from norm8332's "Easy Print" 2600 shell (Fujiversal-Atari2600-CartShell.scad).

Flashing

  • ESP32-S3: USB-C (CP2102N, auto-program): pio run -e fujiversal-atari2600 -t upload.
  • RP2354A, first time: the RP's USB goes only to the S3, so use the SWD pads (TP1 SWCLK, TP2 SWDIO, TP3 GND) with a Raspberry Pi Debug Probe: openocd -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000; program fujivcs.elf verify reset exit".
  • Afterwards: the S3 puts the RP in BOOTSEL (mailbox doorbell, or IO5 low across an IO4 pulse) and writes it over PICOBOOT; by hand, hold BOOTSEL and press RESET.

Firmware changes this board needs (not made here)

On fujinet-firmware 2600-experiment:

  1. An RP2350 board for the cart (e.g. boards/fujivcs2354.cmake/.h): PICO_PLATFORM rp2350, boards/pico2.h-style header, 2 MB flash (stacked).
  2. vcs_pins.h / main.c: drop DIR_PIN (GP26 is unconnected here); keep the output-enable drive/release; give D0-D7 more than the 2 mA drive they had when they only faced a '245 (they now drive the console bus).
  3. Turn the bus pins' pulls off (RP2350 erratum E9), and pick an RP2350 clock (the 250 MHz / 1.15 V RP2040 setting does not carry over as is).
  4. Use GP27 (VSENSE) to idle the bus server while the console is off.
  5. Enable the 1200-baud BOOTSEL reset (pico_usb_reset + PICO_ENABLE_USB_RESET_VIA_BAUD_RATE=1) for the S3's PICOBOOT path.
  6. ESP side: pico_* keys + CONFIG_USB_PICOBOOT_HOST_ENABLED in platformio-fujiversal-atari2600.ini, and the missing data/webui/config/fujiversal-atari2600.yaml.

tools/check_nets.py prints NOTE lines for 1 and 2 until they are done.

Ordering (JLCPCB)

  • PCB: 4 layers, 1.6 mm, ENIG, gold fingers: yes, bevel 30 degrees, upload exports/jlcpcb/Fujiversal-Atari2600-Rev1-gerbers.zip.
  • Assembly: Standard PCBA (gold fingers need it), top side only: BOM-JLCPCB.csv + CPL-JLCPCB.csv (82 parts). The board is narrower than JLC's 70 mm single-board minimum, so let JLC add the edge rails (not on the finger edge). Three fiducials are on the board.
  • CPL: rotations and origins are corrected per footprint against the EasyEDA footprint of each LCSC part (tools/audit/jlc/jlc_rotations.json; ESP32-S3 origin +3.62 mm, USB-C -1.41 mm). Check pin-1 marks in JLC's placement preview anyway.
  • Via-in-pad: the RP2354A and CP2102N exposed pads carry thermal vias. Choose epoxy-filled and capped vias if offered at a sensible price.
  • Stock (2026-10-06): every part in JLC stock; 17 extended parts.

Regenerating

KiCad 10.0.6, Python 3 (numpy), Java + Freerouting 2.4.1 (~/.local/share/freerouting/freerouting-2.4.1.jar), the firmware tree at ~/Workspace/fn-2600 (or $FUJINET_FIRMWARE). tools/build_all.sh runs the schematic stage; LAYOUT=1 tools/build_all.sh adds the board (about 12 minutes):

sh
python3 tools/harvest_symbols.py   # stock KiCad symbols -> tools/symcache.sexpr
python3 tools/make_edge_fp.py      # 2x12 finger footprint
python3 tools/make_fp_extra.py     # SOT-23-5, fiducial
python3 tools/gen_sch.py           # design.py + sch_layout.py -> root + 4 wired sheets; netlist parity
kicad-cli sch erc --severity-all --exit-code-violations Fujiversal-Atari2600-Rev1.kicad_sch -o /dev/null
python3 tools/check_nets.py        # netlist vs the fn-2600 firmware headers
python3 tools/gen_pcb.py           # outline, placement, RP regulator graft, plane islands, fan-out, rules
bash tools/route_board.sh          # Freerouting, A* finisher, tidy, GND stitching, 3D models, silk, DRC gate
python3 tools/export.py            # BOM, JLC BOM + CPL, gerbers, schematic PDF, SVGs, renders

Audit (kicad-happy)

docs/design-review-rev1.md is the datasheet-backed review (schematic + PCB). analysis/ (gitignored) holds the analyzer runs and analysis/deep_review.json; tools/audit/ holds the computations it cites (margins.py), the deep-review generator, the PCB audit runner and the JLC rotation table. .kicad-happy.json records the intentional findings and why.

sh
python3 <kicad-happy>/skills/lcsc/scripts/sync_datasheets_lcsc.py Fujiversal-Atari2600-Rev1.kicad_sch
python3 <kicad-happy>/skills/kicad/scripts/analyze_schematic.py Fujiversal-Atari2600-Rev1.kicad_sch --analysis-dir analysis/
bash tools/audit/run_pcb_audit.sh  # PCB, cross, EMC, thermal, SPICE, gerbers, summary
python3 tools/audit/make_deep_review.py && python3 <kicad-happy>/skills/kicad/review/scripts/deep_review_gate.py analysis/deep_review.json --analysis-dir analysis/

Status

Rev1, generated 2026-10-06. Not built or tested on hardware.

CheckResult
Schematic lint + netlist parity73 nets match design.py
ERC (--severity-all)0 violations
tools/check_nets.py290 / 290 (NOTE: firmware not yet ported to the RP2350)
DRC (--refill-zones --schematic-parity)0 errors, 0 unconnected, 0 parity; 4 warnings (the ESP32 module's silkscreen meets the top edge it sits flush with)
Routing100 %, 339 vias (117 GND stitching)
Connector alignment (2026-10-13)The USB-C (J3) moved 1.0 mm to HRO's recommended PCB-edge position (its face had sat 0.55 mm inside the board, where a plug's overmold meets the PCB edge), and the microSD / USB-C 3D models were re-seated on their footprints. DRC: no new findings (review, "Post-layout change")
kicad-happyschematic 0 errors; SPICE 16/16 pass; DFM (JLC standard tier) 0 violations; Deep Review 19/19 verified; dispositions in the review
Shellclamshell: both halves render 2-manifold in OpenSCAD; cart shell: front, rear and holder render 2-manifold, the board/part interference check is empty, outside faces match norm8332's STLs within 0.3 mm
LCSC / JLCevery part in stock

Bring-up checklist (not verifiable in CAD)

  1. Fit in a real 2600 (heavy sixer, 4-switch, Jr, 7800): fingers seat, shell clears the slot surround. For the cart shell, measure an original cart's edge recess first (edge_recess, see case/case-spec.md).
  2. Console 5 V at finger 23 under WiFi bursts, especially on a Jr.
  3. Power-up: scope +3V3_RP against CONS_5V at console power-on (IOVDD must lead the bus).
  4. Bus timing: address -> data at the edge against the 6507 read window (~500 ns budget); D0-D7 must be released before the address changes.
  5. Back-power: USB-C only, console off: the console must stay dead.
  6. RESET returns to the browser; BOOTSEL + RESET enumerates the RP (VID 0x2E8A) on the S3.
  7. VSENSE reads high with the console on, low on USB only.
  8. microSD card-detect polarity on IO42, then set PIN_CARD_DETECT.
  9. WiFi RSSI inside the shell (antenna flush with the edge, reduced side clearance).
  10. JLC placement preview: pin-1 marks on every IC, LED and diode.

Provenance and license

CERN-OHL-W-2.0.

  • RP2350 core-regulator corner (parts placement and copper): Raspberry Pi RP2350A minimal design (RPI-RP2350A-MINIMAL_R4-S1, MIT, tools/RPI-MINIMAL-LICENSE.txt), the layout the RP2350 datasheet (6.3.8) says to follow.
  • Edge geometry and orientation: the FujiPlusCart prototype in this repository (via Rev0's make_edge_fp.py).
  • Generator pipeline: NES/FujiNet-NES-Rev0/tools (schematic drawing, routing tools), with Rev0's 2600 outline and checks.
  • Cartridge shell (case/Fujiversal-Atari2600-CartShell.scad): re-modelled from "Atari 2600 Cartridge Shell - Easy Print" by norm8332 (https://www.thingiverse.com/thing:1790785, Creative Commons Attribution); changes listed in the file header and case/case-spec.md.
  • Symbols and footprints: official KiCad libraries (CC-BY-SA 4.0 with exception), Raspberry Pi's RP2350A footprint, the TF-015 footprint from LCSC/EasyEDA; 3D models listed in 3d/README.md.

Files

PathContents
Fujiversal-Atari2600-Rev1.kicad_pro/.kicad_sch/.kicad_pcb/.kicad_druKiCad 10 project: root + edge-rp2354a, esp32s3-sd, usb-uart, power
Fujiversal-Atari2600.kicad_sym, Fujiversal-Atari2600.pretty/, 3d/project libraries and models
Fujiversal-Atari2600-Rev1-BOM.csvgrouped BOM, MPN + LCSC on every line
exports/jlcpcb/gerbers zip, BOM-JLCPCB.csv, CPL-JLCPCB.csv
docs/schematic PDF, layout SVGs, 3D renders, design-review-rev1.md
case/OpenSCAD shells (clamshell + full-size cart), generated anchors, case-spec.md
datasheets/manifest.jsondatasheet sources (PDFs gitignored)
tools/the generator pipeline; tools/audit/ the review tooling

Parts

145
QtyValueFootprintReferences
28100nFFujiNet-5200:C_0603_1608MetricC2, C10, C13, C14, C15, C17, C18, C19, C20, C26, C28, C29, C32, C34, C36, C37 +12
1022uFFujiNet-5200:C_0805_2012MetricC3, C11, C12, C21, C22, C23, C44, C45, C47, C48
610kFujiNet-5200:R_0603_1608MetricR4, R5, R6, R13, R21, R26
51kFujiNet-5200:R_0603_1608MetricR9, R14, R15, R18, R20
54.7kFujiNet-5200:R_0603_1608MetricR3, R22, R24, R25, R29
4100kFujiNet-5200:R_0603_1608MetricR7, R8, R23, R28
410uFFujiNet-5200:C_0603_1608MetricC5, C24, C42, C51
41uFFujiNet-5200:C_0603_1608MetricC1, C8, C33, C35
44.7uFFujiNet-5200:C_0603_1608MetricC7, C16, C25, C27
3ESD5Z5.0T1GFujiNet-5200:D_SOD-523D1, D2, D3
3Fiducial_1mm_Mask2mmFujiNet-5200:Fiducial_1mm_Mask2mmFID1, FID2, FID3
3MountingHole_3.2mm_NPTHFujiNet-5200:MountingHole_3.2mm_NPTHH1, H2, H3
215pFFujiNet-5200:C_0603_1608MetricC30, C31
222kFujiNet-5200:R_0603_1608MetricR10, R27
227RFujiNet-5200:R_0603_1608MetricR16, R17
22N7002FujiNet-5200:SOT-23Q1, Q2
25.1kFujiNet-5200:R_0603_1608MetricR1, R2
2BAT54CFujiNet-5200:SOT-23D5, D9
2GNDFujiNet-5200:TestPoint_Pad_D1.5mmTP6, TP12
2SS34FujiNet-5200:D_SMAD4, D8
1+3V3FujiNet-5200:TestPoint_Pad_D1.5mmTP1
1+3V3_RPFujiNet-5200:TestPoint_Pad_D1.5mmTP11
1+5VFujiNet-5200:TestPoint_Pad_D1.5mmTP2
1/EN40FujiNet-5200:TestPoint_Pad_D1.5mmTP8
1/EN80FujiNet-5200:TestPoint_Pad_D1.5mmTP9
1/OE1FujiNet-5200:TestPoint_Pad_D1.5mmTP10
1/OE2FujiNet-5200:TestPoint_Pad_D1.5mmTP13
10.35AFujiNet-5200:Fuse_1206_3216MetricF1
112MHzFujiNet-5200:Crystal_SMD_3225-4Pin_3.2x2.5mmY1
12.2RFujiNet-5200:R_0603_1608MetricR30
13.3uHFujiNet-5200:RPI_L_AOTA-B201610S3R3L2
1330RFujiNet-5200:R_0603_1608MetricR19
133RFujiNet-5200:R_0603_1608MetricR12
14.7uHFujiNet-5200:L_Sunlord_SWPA4030SL3
147kFujiNet-5200:R_0603_1608MetricR11
14x10kFujiNet-5200:R_Array_Convex_4x0603RN1
16.8uHFujiNet-5200:L_Sunlord_SWPA4030SL1
174HCT08FujiNet-5200:SOIC-14_3.9x8.7mm_P1.27mmU8
174HCT14FujiNet-5200:SOIC-14_3.9x8.7mm_P1.27mmU9
174HCT541FujiNet-5200:TSSOP-20_4.4x6.5mm_P0.65mmU7
174LVC1G17FujiNet-5200:SOT-353_SC-70-5U11
1AO3401AFujiNet-5200:SOT-23Q3
1AP2112K-3.3FujiNet-5200:SOT-23-5U6
1AP63203WUFujiNet-5200:TSOT-23-6U4
1AP63205WUFujiNet-5200:TSOT-23-6U10
1Atari5200_Cart_Edge_36FujiNet-5200:Atari5200_Cart_Edge_36J1
1BOOTSELFujiNet-5200:SW_SPST_TS-1187ASW2
1CONS_5VFujiNet-5200:TestPoint_Pad_D1.5mmTP17
1CP2102N-A02-GQFN28FujiNet-5200:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mmU2
1DBG UARTFujiNet-5200:PinHeader_1x03_P2.54mm_VerticalJ4
1DVDDFujiNet-5200:TestPoint_Pad_D1.5mmTP3
1ESP32-S3-WROOM-1-N16R8FujiNet-5200:ESP32-S3-WROOM-1U1
1ILKFujiNet-5200:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mmJP1
1PHI2FujiNet-5200:TestPoint_Pad_D1.5mmTP15
1PRE5VFujiNet-5200:TestPoint_Pad_D1.5mmTP16
1PWR_OKFujiNet-5200:TestPoint_Pad_D1.5mmTP14
1RAWDCFujiNet-5200:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mmJP2
1RAWDCFujiNet-5200:TestPoint_Pad_D1.5mmTP18
1RESETFujiNet-5200:SW_SPST_TS-1187ASW1
1RP2354BFujiNet-5200:QFN-80-1EP_10x10mm_P0.4mm_EP3.4x3.4mmU5
1RUNFujiNet-5200:TestPoint_Pad_D1.5mmTP7
1S3_BOOTFujiNet-5200:SW_SPST_TS-1187ASW4
1S3_RSTFujiNet-5200:SW_SPST_TS-1187ASW3
1SWCLKFujiNet-5200:TestPoint_Pad_D1.5mmTP4
1SWDIOFujiNet-5200:TestPoint_Pad_D1.5mmTP5
1UMH3NFujiNet-5200:SOT-363_SC-70-6U3
1USB-CFujiNet-5200:USB_C_Receptacle_HRO_TYPE-C-31-M-12J2
1WS2812B-2020-V6FujiNet-5200:LED_WS2812B-2020_PLCC4_2.0x2.0mmD6
1microSDFujiNet-5200:TF-SMD_TF-015J3
1redFujiNet-5200:LED_0603_1608MetricD7

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  • 2 layers58.2 × 60 mmInty FujiCard, the printed circuit board in 3D

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Questions

How big is the FujiNet-5200-Rev0 PCB?

It measures 84 × 98 mm and has 6 copper layers, 1.6 mm thick.

What parts does the FujiNet-5200-Rev0 use?

145 parts, built around the RP2354B, SN74HCT541PWRE4, 74LVC1G17GW,125-JSM and ESP32-S3-WROOM-1-N16R8. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the FujiNet-5200-Rev0 KiCad files?

From the FujiNetWIFI/fujinet-hardware repository on GitHub, at the commit this page was made from: the board is ATARI-5200/FujiNet-5200-Rev0/FujiNet-5200-Rev0.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.

Can I use the FujiNet-5200-Rev0 design in my own project?

Its repository states no licence, so its author keeps all rights: ask FujiNetWIFI before reusing the design.