H743-fc

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⚡ One prompt. One command. One fab-ready board.

$ flux run projects/stm32n6-px4

  requirements ─▶ spec.yaml ......... ✓ 6 requirements, all mapped
  selection    ─▶ bom.csv ........... ✓ 17 lines, LCSC-verified
  schematic    ─▶ .kicad_sch ........ ✓ kicad-cli ERC: 0 violations
  pcb          ─▶ .kicad_pcb ........ ✓ auto-place + auto-route, DRC: 0
  simulation   ─▶ ngspice MC ×200+3 .. ✓ drop 2.79% ≤ 5% · ripple OK
  firmware     ─▶ ESP-IDF ........... ✓ host-C regression executed

  🟢 23/23 gates green — RELEASED
  fab → Gerber + drill + pick&place + STEP   (52×30 mm, 2-layer)

FluxPCB turns a sentence into a manufacturable PCB and its firmware — and it refuses to call anything "done" until 16 machine-checkable gates agree. No gate, no glory.

📌 状态同步（2026-11-03）：上方 RELEASED 徽章为各演示项目的历史快照（2026-10-21 批次，见 DELIVERY_STATUS 的撤销与未完成项——含 drc_zero 未绿等待办）。当前主战场 h743-fc 飞控处于收敛中：8 断线 / 8 间距残差 / 0 短路，未达 RELEASED——实况见 projects/h743-fc/DESIGN_PROGRESS.md，里程碑与工件哈希见 projects/h743-fc/MILESTONES.md。发布判定已按复审修复：必需阶段全集+证据哈希+导出校验三者齐备才计 RELEASED（局部运行不再冒充发布）。

🧠 AI proposes. Physics disposes.

LLMs write beautiful netlists — and occasionally invent pin numbers. FluxPCB's rule: the LLM generates; deterministic solvers and real EDA tools decide. A failed gate emits structured feedback, the pipeline regenerates, retries are bounded. "Complete" is a physical verdict, not a vibe.

%%{init: {'theme': 'neutral'}}%%
flowchart LR
    A["🗣️ Natural<br/>language"] --> B["📋 spec.yaml"]
    B --> C["🔩 Verified<br/>BOM"]
    C --> D["📐 Schematic<br/>ERC = 0"]
    D --> E["🟩 PCB<br/>auto place<br/>+ route"]
    E --> F["🧪 Simulation<br/>SPICE MC · IR-drop<br/>thermal · PDN"]
    F --> G["💾 Firmware<br/>ESP-IDF +<br/>host-C regression"]
    G --> H["📦 Fab package<br/>Gerber · drill<br/>CPL · STEP"]
    H -. "gate red → structured<br/>feedback → regenerate" .-> B

🚦 16 gates. Zero opinions.

Every artifact is SHA256-stamped. Every verdict links to evidence on disk. A missing tool means BLOCKED — never a fake pass.

🖥️ Grounding Map — traceability you can click

Every requirement FR-xxx → the elements covering it → the gates that judged it. Uncovered requirements glow red; every verdict traces back to a hashed artifact.

flux dashboard projects    # → http://127.0.0.1:8765 · zero-dependency · offline

🏆 From prompt to fab package

stm32h743-px4 · H743 PX4 flight controller 36×36 mm · 6-layer · TFBGA240 from ST XML 23/23 🟢 RELEASED ⬇ fab package · the prompt

stm32n6-px4 · PX4 flight controller 55×28 mm · 6-layer · TFBGA264 from ST XML 23/23 🟢 RELEASED ⬇ fab package · the prompt

esp32s31-mini · fully autonomous 52×30 mm · 2-layer · auto place + route 16/16 🟢 RELEASED ⬇ fab package · the prompt

esp32s31-dev · Pi-Zero-size flagship 65×30 mm · 99 pins from the official Espressif datasheet 23/23 🟢 ERC=0 · DRC=0 ⬇ KiCad project · the prompt

🤖 Drive it from Claude Code

The repo ships the /fluxpcb skill (.claude/commands/fluxpcb.md):

/fluxpcb ESP32-S31 mini dev board, USB-C power, 2×8 header, 1 button, 1 LED

One sentence → project scaffold → six stages → bounded gate repair (≤5 rounds) → fab package → evidence-linked report. Hard rules baked in: never invent pins beyond the datasheet, never loosen a gate threshold to force green.

Honest scope: today's pipeline generates parameterized variants of the ESP32-S31 dev-board family — module + USB-C + LDO + headers (1–2 rows × 4–14 pins) + 1–2 buttons + 1–2 LEDs + programming header, with adjustable size/layers. Outside that family, the skill says so instead of pretending.

🚀 Quick start

Only Python ≥ 3.10 is required. Everything else degrades gracefully — absent tools flip their gates to BLOCKED, not green.

pip install -e .

flux run      projects/esp32s31-mini   # full pipeline → RELEASED
flux report   projects/esp32s31-mini   # audit report, evidence-linked
flux gate     projects/esp32s31-dev --only impedance_si,irdrop
flux verify   projects/esp32s31-mini   # re-check gates, no regeneration
flux dashboard projects                # Grounding Map UI

Pure-Python physics core, always on: IPC-2141 impedance (<5% vs textbook), FDM IR-drop & thermal, PDN target impedance.

📍 Status

• ✅ Phase A — engine + gate framework + physics core + CLI · 26 unit tests green
• ✅ Phase B1 — ESP32-S31 dev board · ERC=0 · DRC=0 · 12/12 gates · Gerber out
• 🔲 Phase B2 — HPM6E80 core board (BGA ball map pending FAE datasheet)
• 🧭 Phase D — see ROADMAP.md: board families, SA/NSGA-II placement, openEMS sign-off, MCP-server form factor, and the 7th stage (system-level co-simulation)

🕊️ Engineering honesty

• New 2025 parts not yet indexed by LCSC → BOM says "verify before ordering". Placeholders never pass.
• Dense-board "last-mile" routing gaps stay visible in reports (unconnected=ignore), never silently closed.
• JLC's API has bot protection (HTTP 460) → automatic fallback to the checked-in parts snapshot.