4 layers170 × 100 mm
TLV9362ID
Texas InstrumentsExtended
-20V~-2.25V、2.25V~20V -40℃~+125℃ 1.25uV/℃ 10.6MHz 10pA 10pA 110dB 2 2.6mA 25V/us 4.5V~40V 400uV 60mA 6nV/√Hz@1kHz ESD protection、EMI filtering/RF suppression Rail-to-rail output SOIC-8 Operational Amplifier ROHS
- Part id
- ti/TLV9362ID
- Category
- Operational Amplifier
- Package
- SOIC-8
- Pins
- 8
- In stock
- 195 at JLCPCB (C4367884)
- Used on
- 4 open-source boards
Overview
The TLV9362ID is an operational Amplifier made by Texas Instruments in a SOIC-8 package with 8 pins. -20V~-2.25V、2.25V~20V -40℃~+125℃ 1.25uV/℃ 10.6MHz 10pA 10pA 110dB 2 2.6mA 25V/us 4.5V~40V 400uV 60mA 6nV/√Hz@1kHz ESD protection、EMI filtering/RF suppression Rail-to-rail output SOIC-8 Operational Amplifier ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:HT4560BRZ, from EasyEDA) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 195 are in stock at JLCPCB (part C4367884). 4 open-source boards in 3 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
10- Supply, least
- 4.5 V · V+ – V–, recommended operating min · p. 6
- Supply, most
- 40 V · V+ – V–, recommended operating max · p. 6
- Supply, absolute maximum
- 42 V · V+ – V–, absolute maximum · p. 6
- Works from
- -40 °C · specified operating ambient min · p. 6
- Works up to
- 125 °C · specified operating ambient max · p. 6
- Junction, hottest
- 150 °C · junction temperature absolute maximum · p. 6
- Takes working
- 5.2 mA · sum of two amplifiers' typical quiescent currents, IO = 0 A · p. 9
- Junction to air (D (SOIC))
- 131 K/W · junction-to-ambient thermal resistance · p. 7
- Junction to case (D (SOIC))
- 73 K/W · junction-to-case top thermal resistance · p. 7
- Junction to board (D (SOIC))
- 74.5 K/W · junction-to-board thermal resistance · p. 7
What it is and has
9- Input offset voltage
- ±400 µV · p. 1
- Input offset voltage drift
- ±1.25 µV/°C · p. 1
- Common-mode rejection
- 110 dB · p. 1
- Input bias current
- ±10 pA · p. 1
- Output
- Rail-to-rail · p. 1
- Gain-bandwidth product
- 10.6 MHz, unity-gain stable · p. 1
- Slew rate
- 25 V/µs · p. 1
- EMI filtering
- Integrated electromagnetic interference filtering · p. 18
- Protection
- Thermal protection turns off output drive above 170°C · p. 18
Specifications
57| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage VS | VS = (V+) – (V–); over operating ambient temperature range | min 0 · max 42 V | 6 |
| Signal input pins | Current | min -10 · max 10 mA | 6 |
| Operating ambient temperature TA | min -55 · max 150 °C | 6 | |
| Junction temperature TJ | max 150 °C | 6 | |
| Storage temperature Tstg | min -65 · max 150 °C | 6 | |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; ±2500 V | max 2500 V | 6 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002; ±1500 V | max 1500 V | 6 |
| Supply voltage, (V+) – (V–) VS | over operating ambient temperature range | min 4.5 · max 40 V | 6 |
| Specified temperature TA | min -40 · max 125 °C | 6 | |
| Junction-to-ambient thermal resistance RθJA | TLV9362, D (SOIC), 8 PINS | typ 131 °C/W | 7 |
| Junction-to-case (top) thermal resistance RθJC(top) | TLV9362, D (SOIC), 8 PINS | typ 73 °C/W | 7 |
| Junction-to-board thermal resistance RθJB | TLV9362, D (SOIC), 8 PINS | typ 74.5 °C/W | 7 |
| Junction-to-top characterization parameter ψJT | TLV9362, D (SOIC), 8 PINS | typ 25 °C/W | 7 |
| Junction-to-board characterization parameter ψJB | TLV9362, D (SOIC), 8 PINS | typ 73.8 °C/W | 7 |
| Input offset voltage VOS | VCM = V–; TA = 25°C; typical ±0.4 mV, maximum ±1.7 mV | typ 0.4 · max 1.7 mV | 8 |
| Input offset voltage VOS | VCM = V–; TA = –40°C to 125°C; maximum ±2 mV | max 2 mV | 8 |
| Input offset voltage drift dVOS/dT | VCM = V–; TA = –40°C to 125°C; typical ±1.25 uV/℃ | typ 1.25 uV/℃ | 8 |
| Input offset voltage versus power supply PSRR | VCM = V–, VS = 5 V to 40 V; TA = –40°C to 125°C; typical ±1.5 uV/V, maximum ±7.5 uV/V; specified by characterization only | typ 1.5 · max 7.5 uV/V | 8 |
| DC channel separation | typ 1 uV/V | 8 | |
| Input bias current IB | typical ±10 pA | typ 10 pA | 8 |
| Input offset current IOS | typical ±10 pA | typ 10 pA | 8 |
| Input voltage noise EN | f = 0.1 Hz to 10 Hz | typ 6 uVPP | 8 |
| Input voltage noise EN | f = 0.1 Hz to 10 Hz | typ 1 uVRMS | 8 |
| Input voltage noise density eN | f = 1 kHz | typ 8.5 nV/√Hz | 8 |
| Input voltage noise density eN | f = 10 kHz | typ 6 nV/√Hz | 8 |
| Input current noise density iN | f = 1 kHz | typ 100 fA/√Hz | 8 |
| Common-mode rejection ratio CMRR | VS = 40 V, V– < VCM < (V+) – 2 V; TA = –40°C to 125°C | min 95 · typ 110 dB | 8 |
| Common-mode rejection ratio CMRR | VS = 5 V, V– < VCM < (V+) – 2 V; TA = –40°C to 125°C; specified by characterization only | min 75 · typ 85 dB | 8 |
| Open-loop voltage gain AOL | VS = 40 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V; TA = 25°C | min 115 · typ 130 dB | 8 |
| Open-loop voltage gain AOL | VS = 40 V, VCM = VS / 2, (V–) + 0.12 V < VO < (V+) – 0.12 V; TA = –40°C to 125°C | typ 130 dB | 8 |
| Open-loop voltage gain AOL | VS = 5 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V; TA = 25°C; specified by characterization only | min 100 · typ 120 dB | 8 |
| Open-loop voltage gain AOL | VS = 5 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V; TA = –40°C to 125°C; specified by characterization only | typ 120 dB | 8 |
| Gain-bandwidth product GBW | typ 10.6 MHz | 8 | |
| Slew rate SR | VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF | typ 25 V/us | 8 |
| Settling time tS | To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF | typ 0.65 us | 8 |
| Settling time tS | To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF | typ 0.3 us | 8 |
| Settling time tS | To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF | typ 0.86 us | 8 |
| Settling time tS | To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF | typ 0.44 us | 8 |
| Phase margin | G = +1, RL = 10 kΩ, CL = 20 pF | typ 64 ° | 8 |
| Overload recovery time | VIN × gain > VS | typ 170 ns | 8 |
| Total harmonic distortion + noise THD+N | VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ | typ 0.0001 % | 8 |
| Total harmonic distortion + noise THD+N | VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ | typ 120 dB | 8 |
| Total harmonic distortion + noise THD+N | VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω | typ 0.0056 % | 8 |
| Total harmonic distortion + noise THD+N | VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω | typ 85 dB | 8 |
| Total harmonic distortion + noise THD+N | VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω | typ 0.00056 % | 8 |
| Total harmonic distortion + noise THD+N | VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω | typ 105 dB | 8 |
| Voltage output swing from rail | Positive and negative rail headroom; VS = 40 V, RL = no load | typ 10 mV | 9 |
| Voltage output swing from rail | Positive and negative rail headroom; VS = 40 V, RL = 2 kΩ | typ 250 · max 400 mV | 9 |
| Short-circuit current ISC | typical ±60 mA; sudden short at high supply voltage can cause rapid thermal shutdown | typ 60 mA | 9 |
| Quiescent current per amplifier IQ | IO = 0 A; TA = 25°C | typ 2.6 · max 3 mA | 9 |
| Quiescent current per amplifier IQ | IO = 0 A; TA = –40°C to 125°C | max 3.2 mA | 9 |
| EMIRR IN+ | 400 MHz | typ 50 dB | 18 |
| EMIRR IN+ | 900 MHz | typ 56.3 dB | 18 |
| EMIRR IN+ | 1.8 GHz | typ 65.6 dB | 18 |
| EMIRR IN+ | 2.4 GHz | typ 70 dB | 18 |
| EMIRR IN+ | 3.6 GHz | typ 78.9 dB | 18 |
| EMIRR IN+ | 5 GHz | typ 91 dB | 18 |
Pins, by the datasheet
8- 1 OUT1
- Output, channel 1 · p. 4
- 2 IN1–
- Inverting input, channel 1 · p. 4
- 3 IN1+
- Noninverting input, channel 1 · p. 4
- 4 V–
- Negative (lowest) power supply · p. 4
- 5 IN2+
- Noninverting input, channel 2 · p. 4
- 6 IN2–
- Inverting input, channel 2 · p. 4
- 7 OUT2
- Output, channel 2 · p. 4
- 8 V+
- Positive (highest) power supply · p. 4
Open-source boards using it
4- 2 layers50 × 50 mm
- 4 layers91.9 × 56.3 mm
Readout 64x64 regulated
tactilearena/tactilearena.github.io
Scalable high-density tactile arenas for measuring ground-contact forces in freely moving animals: hardware design files, firmware, acquisition and analysis software, and the project website.
66 parts1MIT - 2 layers81 × 85 mm
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Questions
Is there a KiCad symbol and footprint for the TLV9362ID?
Yes. The symbol is EasyEDA_Cloud:HT4560BRZ and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the TLV9362ID?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the TLV9362ID datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the TLV9362ID?
JLCPCB lists it as part C4367884, with 195 in stock; the sellers' links on this page open their listings.
What can replace the TLV9362ID?
Parts like it in the library: the TS922IDT by STMicroelectronics, the LMV358B-SR by 3PEAK, the MC33178D by onsemi and the BUF634AID by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the TLV9362ID?
4 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.