TLV70233PDBV
Texas InstrumentsExtended
-40℃~+125℃@(Tj) 1 260mV@(300mA) 3.3V 300mA 35uA 48uVrms 5.5V 68dB Fixed Positive Under Voltage Lockout、Over Current Protection、Over Temperature Protection、Enable SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS
- Part id
- ti/TLV70233PDBV
- Category
- Voltage Regulators Linear, Low Drop Out (LDO) Regulators
- Package
- SOT-23-5
- Pins
- 5
- In stock
- 3,971 at JLCPCB (C123134)
Overview
The TLV70233PDBV is a voltage Regulators Linear, Low Drop Out (LDO) Regulator made by Texas Instruments in a SOT-23-5 package with 5 pins. -40℃~+125℃@(Tj) 1 260mV@(300mA) 3.3V 300mA 35uA 48uVrms 5.5V 68dB Fixed Positive Under Voltage Lockout、Over Current Protection、Over Temperature Protection、Enable SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS.
PCBKit's library has its KiCad symbol (Pinmap_Generic:Regulator_Linear_1IN_2GND_3EN_4NC_5OUT, from PCBKit's generic symbols) and its footprint (Package_TO_SOT_SMD:SOT-23-5, from KiCad's library), ready for a KiCad board. 3,971 are in stock at JLCPCB (part C123134).
Symbol
Footprint
From the datasheet
12- Supply, least
- 2 V · VIN, recommended operating min · p. 4
- Supply, most
- 5.5 V · VIN, recommended operating max · p. 4
- Supply, absolute maximum
- 6 V · IN, absolute max · p. 4
- Junction, hottest
- 150 °C · Operating virtual junction, absolute max · p. 4
- Takes working
- 35 µA · Ground pin current, typical, IOUT = 0 mA · p. 5
- Takes asleep
- 1 µA · Shutdown ground current, typical, VEN ≤ 0.4 V, VIN = 2 V to 4.5 V · p. 5
- Gives
- 300 mA · IOUT, recommended continuous max · p. 4
- Current limit
- 500 mA · Output current limit, typical, VOUT = 0.9 × VOUT(nom) · p. 5
- Dropout
- 260 mV · Dropout voltage, typical, IOUT = 300 mA · p. 5
- Junction to air (DBV (SOT-23))
- 249.2 K/W · Junction-to-ambient thermal resistance · p. 4
- Junction to board (DBV (SOT-23))
- 85.9 K/W · Junction-to-board thermal resistance · p. 4
- Junction to case (DBV (SOT-23))
- 136.4 K/W · Junction-to-case (top) thermal resistance · p. 4
What it is and has
5- Accuracy
- 2% · p. 1
- Quiescent current
- 35 μA · p. 1
- PSRR
- 68 dB at 1 kHz · p. 1
- Protection
- Thermal shutdown and overcurrent protection · p. 1
- Output discharge
- Active pulldown on TLV702P · p. 1
Around it
2- cap 1 μF
- between IN and GND; Small ceramic capacitor recommended for stability and good transient performance; X5R or X7R recommended. · p. 3
- cap 1 μF
- between OUT and GND; Ceramic capacitor needed for stability; X5R or X7R recommended. Effective capacitance must be at least 0.1 uF after bias and temperature derating; ESR less than 200 mΩ. · p. 3
Specifications
36| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Voltage | IN; over operating junction temperature range | min -0.3 · max 6 V | 4 |
| Voltage | EN; maximum is VIN + 0.3 V or 6.0 V, whichever is smaller | min -0.3 · max 6 V | 4 |
| Voltage | OUT; over operating junction temperature range | min -0.3 · max 6 V | 4 |
| Temperature TJ | Operating virtual junction | min -55 · max 150 °C | 4 |
| Temperature Tstg | Storage | min -55 · max 150 °C | 4 |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; ± rating | min -2000 · max 2000 V | 4 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; ± rating | min -500 · max 500 V | 4 |
| Input voltage VIN | Over operating free-air temperature range | min 2 · max 5.5 V | 4 |
| Output voltage VOUT | Family output-voltage range; over operating free-air temperature range | min 1.2 · max 4.8 V | 4 |
| Output current IOUT | Over operating free-air temperature range | min 0 · max 300 mA | 4 |
| Junction-to-ambient thermal resistance RθJA | DBV (SOT-23), 5 PINS | typ 249.2 °C/W | 4 |
| Junction-to-case (top) thermal resistance RθJC(top) | DBV (SOT-23), 5 PINS | typ 136.4 °C/W | 4 |
| Junction-to-board thermal resistance RθJB | DBV (SOT-23), 5 PINS | typ 85.9 °C/W | 4 |
| Junction-to-top characterization parameter ψJT | DBV (SOT-23), 5 PINS | typ 19.5 °C/W | 4 |
| Junction-to-board characterization parameter ψJB | DBV (SOT-23), 5 PINS | typ 85.3 °C/W | 4 |
| Input voltage range VIN | min 2 · max 5.5 V | 5 | |
| DC output accuracy VOUT | –40°C ≤ TJ ≤ 125°C | min -2 · typ 0.5 · max 2 % | 5 |
| Line regulation ΔVOUT(ΔVIN) | VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA | typ 1 · max 5 mV | 5 |
| Load regulation ΔVOUT(ΔIOUT) | 0 mA ≤ IOUT ≤ 300 mA | typ 1 · max 15 mV | 5 |
| Dropout voltage VDO | VIN = 0.98 × VOUT(nom), IOUT = 300 mA; measured for devices with VOUT(nom) ≥ 2.35 V | typ 260 · max 375 mV | 5 |
| Output current limit ICL | VOUT = 0.9 × VOUT(nom) | min 320 · typ 500 · max 860 mA | 5 |
| Ground pin current IGND | IOUT = 0 mA | typ 35 · max 55 uA | 5 |
| Ground pin current IGND | IOUT = 300 mA, VIN = VOUT + 0.5 V | typ 370 uA | 5 |
| Ground pin current (shutdown) ISHDN | VEN ≤ 0.4 V, VIN = 2 V | typ 400 nA | 5 |
| Ground pin current (shutdown) ISHDN | VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V, TJ = –40°C to +85°C | typ 1 · max 2 uA | 5 |
| Power-supply rejection ratio PSRR | VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz | typ 68 dB | 5 |
| Output noise voltage Vn | BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA | typ 48 uVRMS | 5 |
| Start-up time tSTR | COUT = 1 uF, IOUT = 300 mA; time from EN assertion to 0.98 × VOUT(nom) | typ 100 us | 5 |
| Enable pin high (enabled) VEN(high) | Maximum is VIN | min 0.9 V | 5 |
| Enable pin low (disabled) VEN(low) | min 0 · max 0.4 V | 5 | |
| Enable pin current IEN | VIN = VEN = 5.5 V | typ 0.04 uA | 5 |
| Undervoltage lockout UVLO | VIN rising | typ 1.9 V | 5 |
| Active pulldown resistance (TLV702P only) RDISCHARGE | VEN = 0 V; TLV702P | typ 120 Ω | 5 |
| Thermal shutdown temperature Tsd | Shutdown, temperature increasing | typ 165 °C | 5 |
| Thermal shutdown temperature Tsd | Reset, temperature decreasing | typ 145 °C | 5 |
| Operating junction temperature TJ | min -40 · max 125 °C | 5 |
Pins, by the datasheet
5- 1 IN
- Input supply; a small 1-uF ceramic capacitor to ground is recommended for stability and transient performance. · p. 3
- 2 GND
- Ground pin. · p. 3
- 3 EN
- Enable above 0.9 V; shutdown below 0.4 V. TLV702P discharges the output through an internal 120-Ω resistor during shutdown. · p. 3
- 4 NC
- No connection; may be tied to ground to improve thermal dissipation. · p. 3
- 5 OUT
- Regulated output; a small 1-uF ceramic capacitor to ground is needed for stability. · p. 3
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Questions
Is there a KiCad symbol and footprint for the TLV70233PDBV?
Yes. The symbol is Pinmap_Generic:Regulator_Linear_1IN_2GND_3EN_4NC_5OUT and the footprint Package_TO_SOT_SMD:SOT-23-5, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the TLV70233PDBV?
SOT-23-5, with 5 pins. Its footprint is drawn on this page.
Where is the TLV70233PDBV datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the TLV70233PDBV?
JLCPCB lists it as part C123134, with 3,971 in stock; the sellers' links on this page open their listings.
What can replace the TLV70233PDBV?
Parts like it in the library: the ME6211C33M5G-N by MICRONE, the SPX3819M5-L-3-3/TR by MaxLinear, the RT9013-33GB by RICHTEK and the XC6219B332MR by UMW. Check their datasheets: a part that fits the footprint may still differ in its ratings.