

Overview
The P82B96D is a signal Buffers, Repeaters, Splitter made by Texas Instruments in a SOIC-8 package with 8 pins. -40℃~+85℃ 2 2-Wire Bus 2-Wire Bus 2V~15V 4pF 70ns Buffer SOIC-8 Signal Buffers, Repeaters, Splitters ROHS.
PCBKit's library has its KiCad symbol (Interface_Expansion:P82B96, from KiCad's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 519 are in stock at JLCPCB (part C2652363). 14 open-source boards in 7 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
10- Supply, least
- 2 V · VCC, recommended operating minimum · p. 5
- Supply, most
- 15 V · VCC, recommended operating maximum · p. 5
- Supply, absolute maximum
- 18 V · VCC, absolute maximum · p. 5
- Works from
- -40 °C · Operating free-air temperature minimum · p. 5
- Works up to
- 85 °C · Operating free-air temperature maximum · p. 5
- Takes working
- 900 µA · VCC quiescent supply current typical, Sx = Sy = VCC, TA = 25°C · p. 7
- A pin gives at most
- 250 mA · Sx or Sy continuous output current absolute maximum · p. 5
- Junction to air (D (SOIC))
- 109.1 K/W · Junction-to-ambient thermal resistance · p. 5
- Junction to case (D (SOIC))
- 61.6 K/W · Junction-to-case (top) thermal resistance · p. 5
- Junction to board (D (SOIC))
- 48.6 K/W · Junction-to-board thermal resistance · p. 5
What it is and has
3- Function
- I2C compatible dual bidirectional bus buffer · p. 1
- I2C operation
- 400-kHz Fast I2C bus operation · p. 1
- Bus capacitance
- 400 pF on Sx/Sy; up to 4000 pF on Tx/Ty · p. 14
Around it
1- cap approximately 100 nF
- between VCC and GND; Decoupling capacitor; place as close to VCC as possible. · p. 21
Specifications
138| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage on VCC pin VCC | Over operating free-air temperature range | min -0.3 · max 18 V | 5 |
| Voltage on buffered input VI | Sx or Sy (SDA or SCL) | min -0.3 · max 18 V | 5 |
| Voltage on buffered input VI | Rx or Ry | min -0.3 · max 18 V | 5 |
| Voltage on buffered output VO | Sx or Sy (SDA or SCL) | min -0.3 · max 18 V | 5 |
| Voltage on buffered output VO | Tx or Ty | min -0.3 · max 18 V | 5 |
| Continuous output current IO | Sx or Sy | max 250 mA | 5 |
| Continuous output current IO | Tx or Ty | max 250 mA | 5 |
| Continuous current through VCC or GND ICC | max 250 mA | 5 | |
| Operating free-air temperature TA | min -40 · max 85 °C | 5 | |
| Storage temperature Tstg | min -55 · max 125 °C | 5 | |
| Electrostatic discharge V(ESD) | Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -3500 · max 3500 V | 5 |
| Electrostatic discharge V(ESD) | Charged-Device Model (CDM), per JEDEC specification JESD22-C101 | min -1000 · max 1000 V | 5 |
| Electrostatic discharge V(ESD) | Machine Model (MM), per JEDEC specification JESD22-A115-A | min -200 · max 200 V | 5 |
| Supply voltage VCC | min 2 · max 15 V | 5 | |
| Low-level output current IOL | Sx, Sy; VSx, VSy = 1 V, VRx, VRy ≤ 0.42 V | max 3 mA | 5 |
| Low-level output current IOL | Tx, Ty; VSx, VSy = 0.4 V, VTx, VTy = 0.4 V | max 30 mA | 5 |
| Maximum input/output voltage level VIOmax | Sx, Sy; VTx, VTy = 0.4 V | max 15 V | 5 |
| Maximum input/output voltage level VIOmax | Tx, Ty; VSx, VSy = 0.4 V | max 15 V | 5 |
| Low-level input voltage difference VILdiff | Sx, Sy | max 0.4 V | 5 |
| Junction-to-ambient thermal resistance RθJA | D (SOIC), 8 PINS | typ 109.1 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | D (SOIC), 8 PINS | typ 61.6 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | D (SOIC), 8 PINS | typ 48.6 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | D (SOIC), 8 PINS | typ 19.6 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | D (SOIC), 8 PINS | typ 48.2 °C/W | 5 |
| Temperature coefficient of input thresholds ΔV/ΔTIN | Sx, Sy; TA = 25°C; typical at VCC = 2.5 V | typ -2 mV/°C | 6 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 3 mA; TA = 25°C; typical at VCC = 2.5 V | min 0.8 · typ 0.88 · max 1 V | 6 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 2.5 V | min 0.67 · typ 0.73 · max 0.79 V | 6 |
| Temperature coefficient of output low levels ΔV/ΔTOUT | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 2.5 V | typ -1.8 mV/°C | 6 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = 25°C; typical at VCC = 2.5 V | typ 0.9 · max 1.8 mA | 6 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = –40°C to 85°C | max 2 mA | 6 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = 25°C; typical at VCC = 2.5 V | typ 1.7 · max 2.75 mA | 6 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = –40°C to 85°C | max 3 mA | 6 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = 25°C; typical at VCC = 2.5 V | min 7 · typ 18 mA | 6 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = –40°C to 85°C | min 5.5 mA | 6 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 2.5 V, VRx, VRy = high; TA = 25°C | typ 0.1 · max 1 uA | 6 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 2.5 V, VRx, VRy = high; TA = –40°C to 85°C | max 1 uA | 6 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = 25°C; typical at VCC = 2.5 V | min 60 · typ 100 mA | 6 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = –40°C to 85°C | min 60 mA | 6 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 2.5 V, VSx, VSy = high; TA = 25°C | typ 0.1 · max 1 uA | 6 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 2.5 V, VSx, VSy = high; TA = –40°C to 85°C | max 1 uA | 6 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = 25°C; typical at VCC = 2.5 V | typ -1 uA | 6 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = –40°C to 85°C | max 1 uA | 6 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = 25°C; typical at VCC = 2.5 V | typ -1 uA | 6 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = –40°C to 85°C | max 1 uA | 6 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = 25°C; typical at VCC = 2.5 V | typ 1 uA | 6 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = –40°C to 85°C | max 1.5 uA | 6 |
| Input threshold VIT | Sx, Sy; Input logic level high threshold on normal I2C bus; TA = 25°C; typical at VCC = 2.5 V | typ 0.65 · max 0.7 V | 6 |
| Input threshold VIT | Sx, Sy; Input logic level low threshold on normal I2C bus; TA = 25°C; typical at VCC = 2.5 V | min 0.6 · typ 0.65 V | 6 |
| Input/output logic level difference VIOdiff | Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications; TA = 25°C; typical at VCC = 2.5 V | min 100 · typ 150 mV | 6 |
| Input/output logic level difference VIOdiff | Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications; TA = –40°C to 85°C | min 100 mV | 6 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = 25°C | min 1 V | 6 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = –40°C to 85°C | min 1 V | 6 |
| Temperature coefficient of release voltage ΔV/ΔTREL | TA = 25°C; typical at VCC = 2.5 V | typ -4 mV/°C | 6 |
| Input capacitance Cin | Rx, Ry; TA = 25°C; typical at VCC = 2.5 V | typ 2.5 · max 4 pF | 6 |
| Input capacitance Cin | Rx, Ry; TA = –40°C to 85°C | max 4 pF | 6 |
| Temperature coefficient of input thresholds ΔV/ΔTIN | Sx, Sy; TA = 25°C; typical at VCC = 3.3 V | typ -2 mV/°C | 7 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 3 mA; TA = 25°C; typical at VCC = 3.3 V | min 0.8 · typ 0.88 · max 1 V | 7 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 3.3 V | min 0.67 · typ 0.73 · max 0.79 V | 7 |
| Temperature coefficient of output low levels ΔV/ΔTOUT | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 3.3 V | typ -1.8 mV/°C | 7 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = 25°C; typical at VCC = 3.3 V | typ 0.9 · max 1.8 mA | 7 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = 25°C; typical at VCC = 3.3 V | typ 1.7 · max 2.75 mA | 7 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = –40°C to 85°C | max 3 mA | 7 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = 25°C; typical at VCC = 3.3 V | min 7 · typ 18 mA | 7 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = –40°C to 85°C | min 5.7 mA | 7 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 5 V, VRx, VRy = high; TA = 25°C; typical at VCC = 3.3 V | typ 0.1 · max 1 uA | 7 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 5 V, VRx, VRy = high; TA = –40°C to 85°C | max 1 uA | 7 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = 25°C; typical at VCC = 3.3 V | min 60 · typ 100 mA | 7 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = –40°C to 85°C | min 60 mA | 7 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 3.3 V, VSx, VSy = high; TA = 25°C | typ 0.1 · max 1 uA | 7 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 3.3 V, VSx, VSy = high; TA = –40°C to 85°C | max 1 uA | 7 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = 25°C; typical at VCC = 3.3 V | typ -1 uA | 7 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = –40°C to 85°C | max 1 uA | 7 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = 25°C; typical at VCC = 3.3 V | typ -1 uA | 7 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = –40°C to 85°C | max 1 uA | 7 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = 25°C; typical at VCC = 3.3 V | typ 1 uA | 7 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = –40°C to 85°C | max 1.5 uA | 7 |
| Input threshold VIT | Sx, Sy; Input logic-level high threshold on normal I2C bus; TA = 25°C; typical at VCC = 3.3 V | typ 0.65 · max 0.7 V | 7 |
| Input threshold VIT | Sx, Sy; Input logic-level low threshold on normal I2C bus; TA = 25°C; typical at VCC = 3.3 V | min 0.6 · typ 0.65 V | 7 |
| Input/output logic level difference VIOdiff | Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications; TA = 25°C; typical at VCC = 3.3 V | min 100 · typ 150 mV | 7 |
| Input/output logic level difference VIOdiff | Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications; TA = –40°C to 85°C | min 100 mV | 7 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = 25°C | min 1 V | 7 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = –40°C to 85°C | min 1 V | 7 |
| Temperature coefficient of release voltage ΔV/ΔTREL | TA = 25°C; typical at VCC = 3.3 V | typ -4 mV/°C | 7 |
| Input capacitance Cin | Rx, Ry; TA = 25°C; typical at VCC = 3.3 V | typ 2.5 · max 4 pF | 7 |
| Temperature coefficient of input thresholds ΔV/ΔTIN | Sx, Sy; TA = 25°C; typical at VCC = 5 V | typ -2 mV/°C | 8 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 3 mA; TA = 25°C; typical at VCC = 5 V | min 0.8 · typ 0.88 · max 1 V | 8 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 5 V | min 0.67 · typ 0.73 · max 0.79 V | 8 |
| Temperature coefficient of output low levels ΔV/ΔTOUT | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C; typical at VCC = 5 V | typ -1.8 mV/°C | 8 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = 25°C; typical at VCC = 5 V | typ 0.9 · max 1.8 mA | 8 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = 25°C; typical at VCC = 5 V | typ 1.7 · max 2.75 mA | 8 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = –40°C to 85°C | max 3 mA | 8 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = 25°C; typical at VCC = 5 V | min 7 · typ 18 mA | 8 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = –40°C to 85°C | min 6 mA | 8 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 5 V, VRx, VRy = high; TA = 25°C | typ 0.1 · max 1 uA | 8 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = 25°C; typical at VCC = 5 V | min 60 · typ 100 mA | 8 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 5 V, VSx, VSy = high; TA = 25°C | typ 0.1 · max 1 uA | 8 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 5 V, VSx, VSy = high; TA = –40°C to 85°C | max 1 uA | 8 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = 25°C; typical at VCC = 5 V | typ -1 uA | 8 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = 25°C; typical at VCC = 5 V | typ -1 uA | 8 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = 25°C; typical at VCC = 5 V | typ 1 uA | 8 |
| Input threshold VIT | Sx, Sy; Input logic-level high threshold on normal I2C bus; TA = 25°C; typical at VCC = 5 V | typ 0.65 · max 0.7 V | 8 |
| Input threshold VIT | Sx, Sy; Input logic-level low threshold on normal I2C bus; TA = 25°C; typical at VCC = 5 V | min 0.6 · typ 0.65 V | 8 |
| Input/output logic level difference VIOdiff | Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications; TA = 25°C; typical at VCC = 5 V | min 100 · typ 150 mV | 8 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = 25°C | min 1 V | 8 |
| VCC voltage at which all buses are released VIOrel | Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released; TA = –40°C to 85°C | min 1 V | 8 |
| Temperature coefficient of release voltage ΔV/ΔTREL | TA = 25°C; typical at VCC = 5 V | typ -4 mV/°C | 9 |
| Input capacitance Cin | Rx, Ry; TA = 25°C; typical at VCC = 5 V | typ 2.5 · max 4 pF | 9 |
| Temperature coefficient of input thresholds ΔV/ΔTIN | Sx, Sy; TA = 25°C | typ -2 mV/°C | 9 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 3 mA; TA = 25°C | min 0.8 · typ 0.88 · max 1 V | 9 |
| Low-level output voltage VOL | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C | min 0.67 · typ 0.73 · max 0.79 V | 9 |
| Temperature coefficient of output low levels ΔV/ΔTOUT | Sx, Sy; ISx, ISy = 0.2 mA; TA = 25°C | typ -1.8 mV/°C | 9 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = 25°C | typ 0.9 · max 1.8 mA | 9 |
| Quiescent supply current ICC | Sx = Sy = VCC; TA = –40°C to 85°C | max 2 mA | 9 |
| Additional supply current per pin low ΔICC | Tx, Ty; TA = 25°C | typ 1.7 · max 2.75 mA | 9 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = 25°C | min 7 · typ 18 mA | 9 |
| Dynamic output sink capability on I2C bus IIOS | Sx, Sy; VSx, VSy > 2 V, VRx, VRy = low; TA = –40°C to 85°C | min 6.5 mA | 9 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 15 V, VRx, VRy = high; TA = 25°C | typ 0.1 · max 1 uA | 9 |
| Leakage current on I2C bus IIOS | Sx, Sy; VSx, VSy = 15 V, VRx, VRy = high; TA = –40°C to 85°C | max 1 uA | 9 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = 25°C | min 60 · typ 100 mA | 9 |
| Dynamic output sink capability on buffered bus IIOT | Tx, Ty; VTx, VTy > 1 V, VSx, VSy = low on I2C bus = 0.4 V; TA = –40°C to 85°C | min 60 mA | 9 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 15 V, VSx, VSy = high; TA = 25°C | typ 0.1 · max 1 uA | 9 |
| Leakage current on buffered bus IIOT | Tx, Ty; VTx, VTy = VCC = 15 V, VSx, VSy = high; TA = –40°C to 85°C | max 1 uA | 9 |
| Input current from I2C bus II | Sx, Sy; Bus low, VRx, VRy = high; TA = 25°C | typ -1 uA | 9 |
| Input current from buffered bus II | Rx, Ry; Bus low, VRx, VRy = 0.4 V; TA = 25°C | typ -1 uA | 9 |
| Leakage current on buffered bus input II | Rx, Ry; VRx, VRy = VCC; TA = 25°C | typ 1 uA | 9 |
| Input threshold VIT | Sx, Sy; Input logic-level high threshold on normal I2C bus; TA = 25°C | typ 0.65 · max 0.7 V | 9 |
| Input threshold VIT | Sx, Sy; second input logic-level high threshold row, as printed; TA = 25°C | min 0.6 · typ 0.65 V | 9 |
| Input/output logic level difference (5) VIOdiff | VCC = 15 V, TA = 25°C; Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications | min 100 · typ 150 mV | 10 |
| Input/output logic level difference (5) VIOdiff | VCC = 15 V, TA = –40°C to 85°C; Sx, Sy; (VSx output low at 3 mA) – (VSx input high max) for I2C applications | min 100 mV | 10 |
| VCC voltage at which all buses are released VIOrel | TA = 25°C; Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released | min 1 V | 10 |
| VCC voltage at which all buses are released VIOrel | TA = –40°C to 85°C; Sx, Sy, Tx, Ty; Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released | min 1 V | 10 |
| Temperature coefficient of release voltage ΔV/ΔTREL | TA = 25°C | typ -4 mV/°C | 10 |
| Input capacitance Cin | VCC = 15 V, TA = 25°C; Rx, Ry | typ 2.5 · max 4 pF | 10 |
| Input capacitance Cin | VCC = 15 V, TA = –40°C to 85°C; Rx, Ry | max 4 pF | 10 |
| Buffer delay time on falling input tpzl | VCC = 5 V, TA = 25°C, no capacitive loads; VSx (or VSy) = input switching threshold to VTx (or VTy) output falling 50% of VLOAD; RTx pullup = 160 Ω, CTx = 7 pF + board trace capacitance | typ 70 ns | 10 |
| Buffer delay time on rising input tplz | VCC = 5 V, TA = 25°C, no capacitive loads; VSx (or VSy) = input switching threshold to VTx (or VTy) output reaching 50% of VLOAD; RTx pullup = 160 Ω, CTx = 7 pF + board trace capacitance | typ 90 ns | 10 |
| Buffer delay time on falling input tpzl | VCC = 5 V, TA = 25°C, no capacitive loads; VRx (or VRy) = input switching threshold to VSx (or VSy) output falling 50% of VLOAD; RSx pullup = 1500 Ω, CTx = 7 pF + board trace capacitance | typ 250 ns | 10 |
| Buffer delay time on rising input tplz | VCC = 5 V, TA = 25°C, no capacitive loads; VRx (or VRy) = input switching threshold to VSx (or VSy) output reaching 50% of VLOAD; RSx pullup = 1500 Ω, CTx = 7 pF + board trace capacitance | typ 270 ns | 10 |
Pins, by the datasheet
8- 1 Sx
- Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor. · p. 4
- 2 Rx
- Receive signal. Connect to VCC of P82B96 through a pullup resistor. · p. 4
- 3 Tx
- Transmit signal. Connect to VCC of P82B96 through a pullup resistor. · p. 4
- 4 GND
- Ground. · p. 4
- 5 Ty
- Transmit signal. Connect to VCC of P82B96 through a pullup resistor. · p. 4
- 6 Ry
- Receive signal. Connect to VCC of P82B96 through a pullup resistor. · p. 4
- 7 Sy
- Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor. · p. 4
- 8 VCC
- Supply voltage. · p. 4
Ordering codes, by the datasheet
11- P82B96D
- SOIC · 8 pins, package drawing D, quantity 75, operating temperature -40 to 85 °C · p. 23
- P82B96DG4
- SOIC · 8 pins, package drawing D, quantity 75, operating temperature -40 to 85 °C · p. 23
- P82B96DGKR
- VSSOP · 8 pins, package drawing DGK, quantity 2500, operating temperature -40 to 85 °C · p. 23
- P82B96DGKRG4
- VSSOP · 8 pins, package drawing DGK, quantity 2500, operating temperature -40 to 85 °C · p. 23
- P82B96DR
- SOIC · 8 pins, package drawing D, quantity 2500, operating temperature -40 to 85 °C · p. 23
- P82B96DRG4
- SOIC · 8 pins, package drawing D, quantity 2500, operating temperature -40 to 85 °C · p. 23
- P82B96P
- PDIP · 8 pins, package drawing P, quantity 50, operating temperature -40 to 85 °C · p. 23
- P82B96PW
- TSSOP · 8 pins, package drawing PW, quantity 150, operating temperature -40 to 85 °C · p. 23
- P82B96PWG4
- TSSOP · 8 pins, package drawing PW, quantity 150, operating temperature -40 to 85 °C · p. 23
- P82B96PWR
- TSSOP · 8 pins, package drawing PW, quantity 2000, operating temperature -40 to 85 °C · p. 23
- P82B96PWRG4
- TSSOP · 8 pins, package drawing PW, quantity 2000, operating temperature -40 to 85 °C · p. 23
Parameters
16- Current - Supply
- 900uA
- Data Rate
- 400Kbps
- Delay Time
- 70ns
- Features
- Bus capacitance isolation
- Input Capacitance
- 4pF
- Input Type
- 2-Wire Bus
- Number of Channels
- 2
- Operating Temperature
- -40℃~+85℃
- Output Current per Pin(Max)
- 250mA
- Output Type
- 2-Wire Bus
- Thermal Resistance(Junction to Ambient)
- 109.1℃/W
- Thermal Resistance(Junction to Board)
- 48.6℃/W
- Thermal Resistance(Junction to Case)
- 61.6℃/W
- Type
- Buffer
- Voltage - Supply
- 2V~15V
- Voltage - Supply(Absolute Max)
- 18V
Order codes
2- P82B96DRLCSC C2652363
- P82B96DLCSC C2863829
Pinout
8| Pin | Name | Type |
|---|---|---|
| 1 | SDA | Input/output |
| 2 | RXD-SDA | Input |
| 3 | TXD-SDA | Output |
| 4 | GND | Power in |
| 5 | TXD-SCL | Output |
| 6 | RXD-SCL | Input |
| 7 | SCL | Input/output |
| 8 | VCC | Power in |
Open-source boards using it
All 14- 2 layers65 × 58 mm

- 2 layers99.1 × 99.1 mm

Connector test stand
L0czek/rakieta
The starter board provides the ignition impulse to fire the engine. It includes an I2C IO expander and an 8-channel digital comparator to require a correct safety byte/address to be present before firing.
86 parts - 4 layers426 × 182.3 mm

- 2 layers50 × 100 mm

- 2 layers106.7 × 83.8 mm

Controller
Miceuz/triac-bloc
An universal power block based on triac. In essence this is a solid state relay with some bells and whistles
27 parts54 - 2 layers106.7 × 83.8 mm

Controller
Miceuz/triac-bloc
An universal power block based on triac. In essence this is a solid state relay with some bells and whistles
23 parts54 - 2 layers60 × 100 mm

- 2 layers50 × 50 mm

Alimentatore
CarloMara/didactic-octo-PSU
So, @nicogela and I decided to build a LAB PSU, but because we're lazy people and we don't like to carry weight we're tring to unite the high efficiency of the switching topologies to the high stability and low noise of…
67 parts
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<iframe src="https://pcbkit.io/embed/parts/ti/P82B96D" title="P82B96D in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe><img src="https://pcbkit.io/embed/parts/ti/P82B96D.jpg" alt="P82B96D" width="1200" height="900">[](https://pcbkit.io/parts/ti/P82B96D)Questions
Is there a KiCad symbol and footprint for the P82B96D?
Yes. The symbol is Interface_Expansion:P82B96 and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the P82B96D?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the P82B96D datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the P82B96D?
JLCPCB lists it as part C2652363, with 519 in stock; the sellers' links on this page open their listings.
What can replace the P82B96D?
Parts like it in the library: the TCA4311AD by Texas Instruments, the P82B715TD by NXP Semiconductors, the PCA9508D by NXP Semiconductors and the P82B96TD by NXP Semiconductors. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the P82B96D?
14 boards in 7 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
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