OPA2810ID

Q: Is there a KiCad symbol and footprint for the OPA2810ID?

Yes. The symbol is Operational Amplifiers:Operational Amplifier x2 Type4 and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the OPA2810ID?

SOIC-8, with 8 pins. Its footprint is drawn on this page.

Q: Where is the OPA2810ID datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the OPA2810ID?

JLCPCB lists it as part C1849413, with 3,166 in stock; the sellers' links on this page open their listings.

Q: What can replace the OPA2810ID?

Parts like it in the library: the THS4631D by Texas Instruments, the LF253DT by STMicroelectronics, the OPA810ID by Texas Instruments and the AD825ARZ-REEL7 by Analog Devices. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the OPA2810ID?

6 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

Texas InstrumentsExtended

-12V~12V -40℃~+125℃ 100dB 180V/us 1pA 2 2pA 2uV/℃ 3.65mA 4.75V~27V 5.7nV/√Hz@100kHz 500uV 50mA 70MHz Rail-to-Rail Input, Rail-to-Rail Output Short-Circuit Protection、Built-in compensation、High capacitive load driving、ESD protection SOIC-8 FET Input Amplifiers ROHS

Datasheet JLCPCB LCSC

Part id: ti/OPA2810ID
Category: FET Input Amplifiers
Package: SOIC-8
Pins: 8
In stock: 3,166 at JLCPCB (C1849413)
Used on: 6 open-source boards

Overview

The OPA2810ID is a FET Input Amplifier made by Texas Instruments in a SOIC-8 package with 8 pins. -12V~12V -40℃~+125℃ 100dB 180V/us 1pA 2 2pA 2uV/℃ 3.65mA 4.75V~27V 5.7nV/√Hz@100kHz 500uV 50mA 70MHz Rail-to-Rail Input, Rail-to-Rail Output Short-Circuit Protection、Built-in compensation、High capacitive load driving、ESD protection SOIC-8 FET Input Amplifiers ROHS.

PCBKit's library has its KiCad symbol (Operational Amplifiers:Operational Amplifier x2 Type4, from CERN's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 3,166 are in stock at JLCPCB (part C1849413). 6 open-source boards in 3 repositories on GitHub use it.

Symbol

Operational Amplifiers:Operational Amplifier x2 Type4From CERN's library

Footprint

Package_SO:SOIC-8_3.9x4.9mm_P1.27mmFrom KiCad's library

From the datasheet

Supply, least: 4.75 V · VS, recommended operating minimum total supply · p. 4
Supply, most: 27 V · VS, recommended operating maximum total supply · p. 4
Works from: -40 °C · minimum ambient temperature · p. 4
Works up to: 125 °C · maximum ambient temperature · p. 4
Junction, hottest: 150 °C · maximum junction temperature · p. 4
Takes working: 7.2 mA · sum of two channels, typical quiescent current at 10 V, 25°C · p. 7
Takes at most: 9 mA · sum of two channels, max quiescent current at 24 V, –40°C to +125°C · p. 10
A pin gives at most: 40 mA · maximum continuous output current magnitude, TA = –40℃ to +85℃ · p. 4
Junction to air (D (SOIC)): 123.9 K/W · junction-to-ambient thermal resistance · p. 4
Junction to case (D (SOIC)): 56.3 K/W · junction-to-case top thermal resistance · p. 4
Junction to board (D (SOIC)): 69.4 K/W · junction-to-board thermal resistance · p. 4

What it is and has

Amplifier: Dual-channel, rail-to-rail input/output, FET-input · p. 1
Gain-bandwidth product: 70 MHz · p. 1
Small-signal bandwidth: 105 MHz · p. 1
Slew rate: 192 V/µs · p. 1
Input voltage noise: 6 nV/√Hz at 500 kHz · p. 1
Input current noise: 5 fA/√Hz at 10 kHz · p. 1
Input offset: ±1.5 mV maximum · p. 1
Offset drift: ±2 µV/°C typical · p. 1
Amplifier: Dual-channel, FET-input, unity-gain stable voltage-feedback operational amplifier · p. 25
Small-signal unity-gain bandwidth: 105 MHz · p. 25
Voltage noise density: 6 nV/√Hz · p. 25
Protection: Output short-circuit protection · p. 26

Around it

cap 0.01 µF: between VS+ and GND; High-frequency supply decoupling; place within 0.1 inch of the supply pin. · p. 36
cap 2.2 µF: between VS+ and GND; Typical larger supply-decoupling capacitor; may be placed farther away and shared among devices. · p. 36

Specifications

102

Parameter	Conditions	As printed	Page
Junction temperature TJ		max 150 °C	4
Storage temperature Tstg		min -65 · max 125 °C	4
Total supply voltage VS	Over operating free-air temperature range	min 4.75 · max 27 V	4
Ambient temperature TA	25°C is NOM	min -40 · typ 25 · max 125 °C	4
Junction-to-ambient thermal resistance RθJA	OPA2810, D (SOIC), 8 PINS	typ 123.9 °C/W	4
Junction-to-case (top) thermal resistance RθJC(top)	OPA2810, D (SOIC), 8 PINS	typ 56.3 °C/W	4
Junction-to-board thermal resistance RθJB	OPA2810, D (SOIC), 8 PINS	typ 69.4 °C/W	4
Junction-to-top characterization parameter ψJT	OPA2810, D (SOIC), 8 PINS	typ 13.5 °C/W	4
Junction-to-board characterization parameter ψJB	OPA2810, D (SOIC), 8 PINS	typ 68.1 °C/W	4
Open-loop voltage gain AOL	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = 25°C, f = DC, Vo = ±2.5 V	min 108 · typ 120 dB	6
Open-loop voltage gain AOL	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	min 108 dB	6
Input offset voltage VOS	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = 25°C, input and output biased to midsupply	typ 0.1 · max 1.5 mV	6
Input offset voltage VOS	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +85°C	max 2.4 mV	6
Input offset voltage VOS	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	max 2.8 mV	6
Input offset voltage drift	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; T = 25°C	typ 1.5 uV/°C	6
Input offset voltage drift	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	max 13 uV/°C	6
Input bias current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = 25°C	typ 2 · max 20 pA	6
Input bias current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +85°C (4)	typ 20 · max 60 pA	6
Input bias current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C (4)	typ 100 · max 350 pA	6
Input offset current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = 25°C	typ 1 · max 20 pA	6
Input offset current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +85°C	typ 5 pA	6
Input offset current	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	typ 50 pA	6
Common-mode rejection ratio CMRR	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; f = DC, TA = 25°C, VCM = –3 V to +1 V	min 85 · typ 100 dB	6
Common-mode rejection ratio CMRR	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	min 85 dB	6
Differential input capacitance	VS+ = 5 V, VS– = –5 V; In open-loop configuration	typ 0.5 pF	6
Linear output drive (sourcing and sinking) IO(max)	VS+ = 5 V, VS– = –5 V; TA = 25°C, VO = 2.65 V, RL = 51 Ω, VOS < 2 mV	min 52 · typ 75 mA	6
Linear output drive (sourcing and sinking) IO(max)	VS+ = 5 V, VS– = –5 V; TA = –40°C to +125°C, VO = 1.4 V, VOS < 2 mV	min 28 mA	6
Output short-circuit current ISC	VS+ = 5 V, VS– = –5 V; TA = 25°C, TDelay = 5 ms	typ 100 mA	6
Capacitive load drive CL	VS+ = 5 V, VS– = –5 V; TA = 25°C, < 1 dB peaking, RS = 0 Ω	typ 35 pF	6
Operating voltage VS	TA = 25°C	min 4.75 · max 27 V	7
Operating voltage VS	TA = –40°C to +125°C	min 4.75 · max 27 V	7
Quiescent current per channel IQ	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = 25°C	min 3.125 · typ 3.6 · max 4.05 mA	7
Quiescent current per channel IQ	VS+ = 5 V, VS– = –5 V, RL = 1 kΩ; TA = –40°C to +125°C	min 2.9 · max 4.4 mA	7
Power supply rejection ratio PSRR	TA = 25°C, ΔVS = 2 V (6)	min 82 · typ 100 dB	7
Power supply rejection ratio PSRR	TA = –40°C to +125°C	min 82 dB	7
Gain-bandwidth product	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = (VS+) – 1 V	typ 35 MHz	7
Open-loop voltage gain	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = (VS+) – 1 V, f = DC, Vo = 2 V to 4 V	min 80 · typ 100 dB	7
Input-referred voltage noise	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ – 1V, f = 1 MHz	typ 21 nV/√Hz	7
Input offset voltage	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ – 1.5 V, no-load	max 4 mV	7
Input offset voltage	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ – 0.5 V, no-load	max 4.8 mV	7
Input offset voltage	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V; VCM = VS+ – 0.5 V, TA = –40°C to +125°C, no-load	max 6.4 mV	7
Input bias current	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ – 1.5 V	typ 2 · max 20 pA	7
Input bias current	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V; VCM = VS+ – 1.5 V, TA = -40°C to +125°C	typ 0.15 · max 0.5 nA	7
Common-mode rejection ratio	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ - 1.5 V to VS+ – 0.5 V	typ 75 dB	7
Power supply rejection ratio	Auxiliary CMOS input stage; VS+ = 5 V, VS– = –5 V, TA = 25°C; VCM = VS+ – 1.5 V, ΔVS = ±2 V (6)	typ 75 dB	7
Channel-to-channel GBWP mismatch	VS+ = 5 V, VS– = –5 V; TA = 25°C	typ 3 %	7
Channel-to-channel crosstalk	VS+ = 5 V, VS– = –5 V, TA = 25°C; f = 100 kHz	typ -93 dBc	7
Input offset voltage mismatch	VS+ = 5 V, VS– = –5 V; TA = 25°C	typ 0.1 · max 2.5 mV	7
Open-loop voltage gain AOL	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C, f = DC, Vo = ±8 V	min 108 · typ 120 dB	9
Open-loop voltage gain AOL	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	min 108 dB	9
Input offset voltage VOS	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C, input and output biased to midsupply	typ 0.1 · max 1.5 mV	9
Input offset voltage VOS	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +85°C	max 2.4 mV	9
Input offset voltage VOS	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	max 2.8 mV	9
Input offset voltage drift	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C	typ 1.5 uV/°C	9
Input offset voltage drift	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	max 13 uV/°C	9
Input bias current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C	typ 2 · max 20 pA	9
Input bias current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +85°C (4)	typ 20 · max 60 pA	9
Input bias current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C (4)	typ 100 · max 460 pA	9
Input offset current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C	typ 1 · max 20 pA	9
Input offset current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +85°C	typ 5 pA	9
Input offset current	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	typ 50 pA	9
Common-mode rejection ratio CMRR	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; f = DC, TA = 25°C, VCM = ±5 V	min 90 · typ 105 dB	9
Common-mode rejection ratio CMRR	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	min 90 dB	9
Differential input capacitance	VS+ = 12 V, VS– = –12 V; In open-loop configuration	typ 0.5 pF	9
Linear output drive (sourcing and sinking) IO(max)	VS+ = 12 V, VS– = –12 V; TA = 25°C, Vo = 7.25 V, RL = 151 Ω, VOS < 2 mV	min 48 · typ 64 mA	9
Linear output drive (sourcing and sinking) IO(max)	VS+ = 12 V, VS– = –12 V; TA = –40°C to +90°C, Vo = 4.35 V, VOS < 2 mV	min 29 mA	9
Output short-circuit current ISC	VS+ = 12 V, VS– = –12 V; TA = 25°C, TDelay = 5 ms	typ 108 mA	9
Capacitive load drive CL	VS+ = 12 V, VS– = –12 V; TA = 25°C, < 1 dB peaking, RS = 0 Ω	typ 35 pF	9
Quiescent current per channel IQ	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = 25°C	min 3.2 · typ 3.7 · max 4.1 mA	10
Quiescent current per channel IQ	VS+ = 12 V, VS– = –12 V, RL = 1 kΩ; TA = –40°C to +125°C	min 3 · max 4.5 mA	10
Power supply rejection ratio PSRR	TA = 25°C, ΔVS = 2 V (6)	min 90 · typ 105 dB	10
Power supply rejection ratio PSRR	TA = –40°C to +125°C	min 90 dB	10
Gain-bandwidth product	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1 V	typ 35 MHz	10
Open-loop voltage gain	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1 V, f = DC, Vo = 7 V to –7 V	min 80 · typ 95 dB	10
Input-referred voltage noise	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1 V, f = 1 MHz	typ 21 nV/√Hz	10
Input offset voltage	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1.5 V, no-load	max 4 mV	10
Input offset voltage	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 0.5 V, no-load	max 4.8 mV	10
Input offset voltage	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V; VCM = VS+ – 0.5 V, TA = –40°C to +125°C, no-load	max 6.4 mV	10
Input bias current	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1.5 V	typ 2 · max 24 pA	10
Input bias current	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V; VCM = VS+ – 1.5 V, TA = –40°C to +125°C	typ 0.15 · max 1 nA	10
Common-mode rejection ratio	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1.5 V to VS+ – 0.5 V	typ 75 dB	10
Power supply rejection ratio	Auxiliary CMOS input stage; VS+ = 12 V, VS– = –12 V, TA = 25°C; VCM = VS+ – 1.5 V, ΔVS = ±2 V (6)	typ 70 dB	10
Channel-to-channel GBWP mismatch	VS+ = 12 V, VS– = –12 V; TA = 25°C	typ 3 %	10
Channel-to-channel crosstalk	VS+ = 12 V, VS– = –12 V, TA = 25°C; f = 100 kHz	typ -93 dBc	10
Input offset voltage mismatch	VS+ = 12 V, VS– = –12 V; TA = 25°C	typ 0.1 · max 2.5 mV	10
Input bias current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = 25°C	typ 2 · max 20 pA	12
Input bias current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = –40°C to +85°C (4)	typ 20 · max 50 pA	12
Input bias current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = –40°C to +125°C (4)	typ 100 · max 340 pA	12
Input offset current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = 25°C	typ 1 · max 20 pA	12
Input offset current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = –40°C to +85°C	typ 5 pA	12
Input offset current	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = –40°C to +125°C	typ 50 pA	12
Common-mode rejection ratio CMRR	VS+ = 5 V, VS– = 0 V, RL = 1 kΩ; f = DC, TA = 25°C, VCM = 0.75 V to 1.75 V	min 78 · typ 92 dB	12
Common-mode rejection ratio CMRR	VS+ = 5 V, VS– = 0 V, RL = 1 kΩ; TA = –40°C to +125°C	min 75 dB	12
Differential input capacitance	VS+ = 5 V, VS– = 0 V; In open-loop configuration	typ 0.5 pF	12
Linear output drive (sourcing and sinking) IO(max)	TA = 25°C, VO = 1.4 V, RL = 27.5 Ω, VOS < 2 mV, VS+ = 3 V and VS– = –2 V	min 50 · typ 64 mA	12
Linear output drive (sourcing and sinking) IO(max)	TA = -40°C to 125°C, VO = 0.6 V, VOS < 2 mV, VS+ = 3 V and VS– = –2 V	min 22 mA	12
Output short-circuit current ISC	VS+ = 5 V, VS– = 0 V; TA = 25°C, TDelay = 5 ms	typ 96 mA	12
Capacitive load drive CL	VS+ = 5 V, VS– = 0 V; TA = 25°C, < 1 dB peaking, RS = 0 Ω	typ 35 pF	12
Quiescent current per channel IQ	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = 25°C	min 3.05 · typ 3.6 · max 4 mA	12
Quiescent current per channel IQ	VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ; TA = –40°C to +125°C	min 2.8 · max 4.4 mA	12
Power supply rejection ratio PSRR	TA = 25°C, ΔVS = 0.5 V, VCM = 0.5 V (6)	min 80 · typ 100 dB	12
Power supply rejection ratio PSRR	TA = –40°C to +125°C	min 80 dB	12

Pins, by the datasheet

1 VO1: Amplifier 1 output pin. · p. 3
2 VIN1-: Amplifier 1 inverting input pin. · p. 3
3 VIN1+: Amplifier 1 noninverting input pin. · p. 3
4 VS-: Negative power supply pin. · p. 3
5 VIN2+: Amplifier 2 noninverting input pin. · p. 3
6 VIN2-: Amplifier 2 inverting input pin. · p. 3
7 VO2: Amplifier 2 output pin. · p. 3
8 VS+: Positive power supply pin. · p. 3

Ordering codes, by the datasheet

OPA2810IDR: SOIC (D), 8 pins · 2500 units, large tape and reel; operating temperature -40 to 125 °C · p. 40
OPA2810IDR.B: SOIC (D), 8 pins · 2500 units, large tape and reel; operating temperature -40 to 125 °C · p. 40
OPA2810IDT: SOIC (D), 8 pins · 250 units, small tape and reel; operating temperature -40 to 125 °C · p. 40
OPA2810IDT.B: SOIC (D), 8 pins · 250 units, small tape and reel; operating temperature -40 to 125 °C · p. 40

Parameters

Common Mode Rejection Ratio(CMRR): 100dB
Current - Supply: 7.2mA
Current - Supply(Max): 9mA
Dual Supply: -12V~12V
Features: ESD Protection
Gain Bandwidth Product: 70MHz
Ib - Input Bias Current: 2pA
Input Offset Current(Ios): 1pA
Input Offset Voltage Drift(Vos TC): 2uV/℃
Input Voltage Noise Density: 5.7nV/√Hz@100kHz
Junction Temperature(Max): 150℃
Noise density(eN): 5.7nV/√Hz@100kHz
Number of Channels: 2
Operating Temperature: -40℃~+125℃
Output Current: 50mA
Output Current per Pin(Max): 40mA
Quiescent Current: 3.5mA
Quiescent Current(Iq): 3.65mA
Rail To Rail: Rail-to-Rail Input, Rail-to-Rail Output
Single Supply: 4.75V~27V
Slew Rate: 180V/us
Thermal Resistance(Junction to Ambient): 123.9℃/W
Thermal Resistance(Junction to Board): 69.4℃/W
Thermal Resistance(Junction to Case): 56.3℃/W
Voltage - Supply: 4.75V~27V
Vos - Input Offset Voltage: 500uV

Order codes

OPA2810IDRLCSC C1849413
OPA2810IDTLCSC C2864999

Pinout

The pins of the OPA2810ID
Pin	Name	Type
1	OUT	Output
2	IN-	Input
3	IN+	Input
4	V-	Power in
5	IN+	Input
6	IN-	Input
7	OUT	Output
8	V+	Power in

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Parts like it

Questions

Is there a KiCad symbol and footprint for the OPA2810ID?

Yes. The symbol is Operational Amplifiers:Operational Amplifier x2 Type4 and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the OPA2810ID?

SOIC-8, with 8 pins. Its footprint is drawn on this page.

Where is the OPA2810ID datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the OPA2810ID?

JLCPCB lists it as part C1849413, with 3,166 in stock; the sellers' links on this page open their listings.

What can replace the OPA2810ID?

Parts like it in the library: the THS4631D by Texas Instruments, the LF253DT by STMicroelectronics, the OPA810ID by Texas Instruments and the AD825ARZ-REEL7 by Analog Devices. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the OPA2810ID?

6 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

OPA2810ID

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Ordering codes, by the datasheet

Open-source boards using it

Quadrant

Pss

Analog board

Quadrant-2x2

Amod c

Pss baseboard

Parts like it

THS4631D

LF253DT

OPA810ID

AD825ARZ-REEL7

AD8510ARZ-REEL7

ADA4610-2ARZ-R7

TL082AIYDT

TL082BCDT