12 layers280 × 111.2 mm
Fpga candelabra
chipsalliance/rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
738 parts21Apache-2.0
Overview
The LSF0108PW is a translators, Level Shifter made by Texas Instruments in a TSSOP-20 package with 20 pins. -40℃~+125℃ 1 1.8V~5.5V 8 950mV~4.5V Auto Direction Detection Bidirectional Push-Pull、Open Drain TSSOP-20 Translators, Level Shifters ROHS.
PCBKit's library has its KiCad symbol (Logic_LevelTranslator:LSF0108PW, from KiCad's library) and its footprint (Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 24,617 are in stock at JLCPCB (part C190219). 9 open-source boards in 8 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
9- Supply, most
- 5.5 V · Vref_A/B/EN, recommended operating max · p. 5
- Works from
- -40 °C · ambient temperature min · p. 5
- Works up to
- 125 °C · ambient temperature max · p. 5
- Junction, hottest
- 150 °C · junction temperature absolute max · p. 5
- Takes working
- 50 nA · typical supply current, Vref_B = EN = 5.5 V, Vref_A = 4.5 V, no load · p. 6
- Junction to air (PW (TSSOP))
- 108.8 K/W · junction-to-ambient thermal resistance · p. 6
- Junction to case (PW (TSSOP))
- 45.7 K/W · junction-to-case top thermal resistance · p. 6
- Junction to board (PW (TSSOP))
- 61.8 K/W · junction-to-board thermal resistance · p. 6
- Supply, least
- 650 mV · Vref_A, recommended operating min · p. 20
What it is and has
9- Channels
- 8 · p. 13
- Interfaces
- GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI · p. 13
- I/O tolerance
- 5 V · p. 1
- Disabled state
- High-impedance I/O pins for EN low · p. 1
- Pinout
- Flow-through · p. 1
- Latch-up performance
- >100 mA per JESD 17 · p. 1
- Operating temperature
- –40°C to 125°C · p. 1
- Package
- PW (TSSOP, 20), 4.40 mm × 6.50 mm body · p. 1
- Voltage translation
- Bidirectional · p. 1
Around it
4- res 200 kΩ
- between VCCB and Vref_B/EN; Bias resistor; tie EN directly to Vref_B and pull both up to the high-side supply. · p. 11
- cap 0.1 µF
- between Vref_B and GND; Recommended filter capacitor providing a path to ground for high frequency noise. · p. 14
- res 200 kΩ
- between VCCB and Vref_B / EN; Typical bias resistor; connect EN to Vref_B and pull both up to VCCB. · p. 15
- res 1 MΩ
- between VCCB and Vref_A; Typical R1 for single supply translation to reduce current consumption; select R2 using the stated equation. · p. 18
Specifications
71| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Input voltage range VI | Over operating free-air temperature range | min -0.5 · max 7 V | 5 |
| Input-output voltage range VI/O | Over operating free-air temperature range | min -0.5 · max 7 V | 5 |
| Continuous channel current | Over operating free-air temperature range | max 128 mA | 5 |
| Input Clamp Current IIK | VI < 0 | max -50 mA | 5 |
| Junction temperature TJ(Max) | max 150 °C | 5 | |
| Storage temperature Tstg | min -65 · max 150 °C | 5 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -2000 · max 2000 V | 5 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 | min -1000 · max 1000 V | 5 |
| Input-output voltage VI/O | A1, A2 - An, B2 - Bn | min 0 · max 5.5 V | 5 |
| Reference Voltage Vref_A/B/EN | Translation constraints in footnote (1) | min 0 · max 5.5 V | 5 |
| Switch mode enable voltage (Switch mode enable voltage) EN-Switch | Switch mode | min 1.5 · max 5.5 V | 5 |
| Pass switch current IPASS | max 64 mA | 5 | |
| Ambient temperature TA | min -40 · max 125 °C | 5 | |
| Junction-to-ambient thermal resistance RθJA | LSF0108, PW (TSSOP), 20 pins | typ 108.8 °C/W | 6 |
| Junction-to-case (top) thermal resistance RθJC(top) | LSF0108, PW (TSSOP), 20 pins | typ 45.7 °C/W | 6 |
| Junction-to-board thermal resistance RθJB | LSF0108, PW (TSSOP), 20 pins | typ 61.8 °C/W | 6 |
| Junction-to-top characterization parameter ΨJT | LSF0108, PW (TSSOP), 20 pins | typ 10.4 °C/W | 6 |
| Junction-to-board characterization parameter ΨJB | LSF0108, PW (TSSOP), 20 pins | typ 61.1 °C/W | 6 |
| Input clamp voltage VIK | II = -18 mA, VEN = 0 V | min -1.2 · max 0 V | 6 |
| Input leakage current IIH | VI = 5 V, VO = 0 V, VEN = 0 V | min 0.001 · typ 0.5 · max 3 uA | 6 |
| Supply current ICC | Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND | min 0.002 · typ 0.05 · max 1.5 uA | 6 |
| Input capacitance CI(EN) | VI = 3 V or 0 V | typ 40 pF | 6 |
| Off capacitance CIO(off) | VO = 3 V or 0 V, VEN = 0 V | typ 4 · max 6 pF | 6 |
| On capacitance CIO(on) | VO = 3 V or 0 V, VEN = 3 V | typ 10.5 · max 12.5 pF | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 64 mA, Vref_A = 1 V; application connected current source configuration | typ 5 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 64 mA, Vref_A = 1.8 V; application connected current source configuration | typ 4 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 64 mA, Vref_A = 2.5 V; application connected current source configuration | typ 3 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 64 mA, Vref_A = 3.3 V; application connected current source configuration | typ 3 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 20 mA, Vref_A = 0.65 V; application connected current source configuration | typ 15 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 32 mA, Vref_A = 1 V; application connected current source configuration | typ 5 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 32 mA, Vref_A = 1.8 V; application connected current source configuration | typ 4 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 32 mA, Vref_A = 2.5 V; application connected current source configuration | typ 3 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 5 V, IO = 32 mA, Vref_A = 3.3 V; application connected current source configuration | typ 3 Ω | 6 |
| On-state resistance RON | VI = 1.8 V, Vref_B = 5 V, IO = 15 mA, Vref_A = 3.3 V; application connected current source configuration | typ 4 Ω | 6 |
| On-state resistance RON | VI = 1 V, Vref_B = 3.3 V, IO = 10 mA, Vref_A = 1.8 V; application connected current source configuration | typ 7 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 3.3 V, IO = 10 mA, Vref_A = 0.65 V; application connected current source configuration | typ 15 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 3.3 V, IO = 10 mA, Vref_A = 1 V; application connected current source configuration | typ 5 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 1.8 V, IO = 10 mA, Vref_A = 0.65 V; application connected current source configuration | typ 15 Ω | 6 |
| On-state resistance RON | VI = 0 V, Vref_B = 1.8 V, IO = 10 mA, Vref_A = 1 V; application connected current source configuration | typ 6 Ω | 6 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 15 pF; specified by simulation | typ 0.75 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 30 pF; specified by simulation | typ 1.4 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 50 pF; specified by simulation | typ 1.9 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 15 pF; specified by simulation | typ 0.85 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 30 pF; specified by simulation | typ 1.5 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 50 pF; specified by simulation | typ 2 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 15 pF; specified by simulation | typ 0.8 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 30 pF; specified by simulation | typ 1.45 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 50 pF; specified by simulation | typ 2 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 15 pF; specified by simulation | typ 0.9 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 30 pF; specified by simulation | typ 1.55 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VIH = Vref_A + 1, VIL = 0, VM = 0.5Vref_A; CL = 50 pF; specified by simulation | typ 2.1 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 15 pF; specified by simulation | typ 0.9 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 30 pF; specified by simulation | typ 1.55 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 50 pF; specified by simulation | typ 2.1 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 15 pF; specified by simulation | typ 1 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 30 pF; specified by simulation | typ 1.65 ns | 7 |
| High to low propagation delay TPHL | VCCB = 3.3 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 50 pF; specified by simulation | typ 2.2 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 15 pF; specified by simulation | typ 0.8 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 30 pF; specified by simulation | typ 1.35 ns | 7 |
| Low-to-high propagation delay TPLH | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 50 pF; specified by simulation | typ 1.8 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 15 pF; specified by simulation | typ 0.9 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 30 pF; specified by simulation | typ 1.45 ns | 7 |
| High to low propagation delay TPHL | VCCB = 2.5 V, VCCB = VT = Vref_A + 1, Vref_A = VIH, VIL = 0, VM = 0.5Vref_A, RL = 300 Ω; CL = 50 pF; specified by simulation | typ 1.9 ns | 7 |
| reference voltage (A) Vref_A | Vref_A must be the lowest voltage level across all inputs and outputs | min 0.65 V | 14 |
| reference voltage (B) Vref_B | Minimum = Vref_A + 0.8 V | max 5.5 V | 14 |
| input voltage on EN pin VI(EN) | Minimum = Vref_A + 0.8 V | max 5.5 V | 14 |
| pull-up supply voltage VPU | Maximum = Vref_B | min 0 V | 14 |
| reference voltage (A) Vref_A | Vref_A is required to be the lowest voltage level across all inputs and outputs. | min 0.65 · max 5.5 V | 20 |
| reference voltage (B) Vref_B | Minimum: Vref_A + 0.8 V | max 5.5 V | 20 |
| input voltage on EN pin VI(EN) | Minimum: Vref_A + 0.8 V | max 5.5 V | 20 |
| pull-up supply voltage VPU | Maximum: Vref_B | min 0 V | 20 |
Pins, by the datasheet
20- 1 GND
- Ground. · p. 4
- 2 Vref_A
- Reference supply voltage. · p. 4
- 3 A1
- Auto-Bidirectional Data port. · p. 1
- 4 A2
- Auto-Bidirectional Data port. · p. 1
- 5 A3
- Auto-Bidirectional Data port. · p. 1
- 6 A4
- Auto-Bidirectional Data port. · p. 1
- 7 A5
- Auto-Bidirectional Data port. · p. 1
- 8 A6
- Auto-Bidirectional Data port. · p. 1
- 9 A7
- Auto-Bidirectional Data port. · p. 1
- 10 A8
- Auto-Bidirectional Data port. · p. 1
- 11 B8
- Auto-Bidirectional Data port. · p. 1
- 12 B7
- Auto-Bidirectional Data port. · p. 1
- 13 B6
- Auto-Bidirectional Data port. · p. 1
- 14 B5
- Auto-Bidirectional Data port. · p. 1
- 15 B4
- Auto-Bidirectional Data port. · p. 1
- 16 B3
- Auto-Bidirectional Data port. · p. 1
- 17 B2
- Auto-Bidirectional Data port. · p. 1
- 18 B1
- Auto-Bidirectional Data port. · p. 1
- 19 Vref_B
- Reference bias connection; see Section 9 for proper device biasing. · p. 4
- 20 EN
- Enable input; connect to Vref_B and pull up through a 200 kΩ resistor. · p. 4
Ordering codes, by the datasheet
6- LSF0108DGSR
- VSSOP (DGS), 20 pins · 5000 per large tape and reel; operating temperature -40 to 125 °C · p. 22
- LSF0108DGSR.A
- VSSOP (DGS), 20 pins · 5000 per large tape and reel; operating temperature -40 to 125 °C · p. 22
- LSF0108PWR
- TSSOP (PW), 20 pins · 2000 per large tape and reel; operating temperature -40 to 125 °C · p. 22
- LSF0108PWR.A
- TSSOP (PW), 20 pins · 2000 per large tape and reel; operating temperature -40 to 125 °C · p. 22
- LSF0108RKSR
- VQFN (RKS), 20 pins · 3000 per large tape and reel; NIPDAU or NIPDAUAG finish; operating temperature -40 to 125 °C · p. 22
- LSF0108RKSR.A
- VQFN (RKS), 20 pins · 3000 per large tape and reel; NIPDAU finish; operating temperature -40 to 125 °C · p. 22
Parameters
16- Channel Type
- Bidirectional
- Current - Supply
- 50nA
- Features
- Output enable high-impedance
- Interface
- UART
- Junction Temperature(Max)
- 150℃
- Number of Circuits
- 8
- Number of Elements
- 1
- Operating Temperature
- -40℃~+125℃
- Output Type
- Open-drain
- Thermal Resistance(Junction to Ambient)
- 108.8℃/W
- Thermal Resistance(Junction to Board)
- 61.8℃/W
- Thermal Resistance(Junction to Case)
- 45.7℃/W
- Translator Type
- Level translator
- Voltage - Supply
- 650mV~5.5V
- Voltage - Supply(VCCA)
- 950mV~4.5V
- Voltage - Supply(VCCB)
- 1.8V~5.5V
Order codes
1- LSF0108PWRLCSC C190219
Pinout
20| Pin | Name | Type |
|---|---|---|
| 1 | GND | Power in |
| 2 | RefA | Power in |
| 3 | A1 | Input/output |
| 4 | A2 | Input/output |
| 5 | A3 | Input/output |
| 6 | A4 | Input/output |
| 7 | A5 | Input/output |
| 8 | A6 | Input/output |
| 9 | A7 | Input/output |
| 10 | A8 | Input/output |
| 11 | B8 | Input/output |
| 12 | B7 | Input/output |
| 13 | B6 | Input/output |
| 14 | B5 | Input/output |
| 15 | B4 | Input/output |
| 16 | B3 | Input/output |
| 17 | B2 | Input/output |
| 18 | B1 | Input/output |
| 19 | RefB | Power in |
| 20 | EN | Input |
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Is there a KiCad symbol and footprint for the LSF0108PW?
Yes. The symbol is Logic_LevelTranslator:LSF0108PW and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the LSF0108PW?
TSSOP-20, with 20 pins. Its footprint is drawn on this page.
Where is the LSF0108PW datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the LSF0108PW?
JLCPCB lists it as part C190219, with 24,617 in stock; the sellers' links on this page open their listings.
What can replace the LSF0108PW?
Parts like it in the library: the TXS0108EPW by Texas Instruments, the TXB0108PW by Texas Instruments, the SN74GTL2003PW by Texas Instruments and the RS0108YQ20 by Jiangsu RUNIC Tech. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the LSF0108PW?
9 boards in 8 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
Parts like it
8
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