LP2992IM5-3.3
Texas Instruments
-40℃~+125℃@(Tj) 1 16V 250mA 3.3V 30uVrms 45dB@(1kHz) 800nA 850mV@(250mA) Fixed Over Current Protection、Over Temperature Protection、Enable、Short Circuit Protection Positive SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS
Extended
- Category
- Voltage Regulators Linear, Low Drop Out (LDO) Regulators
- Package
- SOT-23-5
- Pins
- 5
Overview
The LP2992IM5-3.3 is a voltage Regulators Linear, Low Drop Out (LDO) Regulator made by Texas Instruments in a SOT-23-5 package with 5 pins. -40℃~+125℃@(Tj) 1 16V 250mA 3.3V 30uVrms 45dB@(1kHz) 800nA 850mV@(250mA) Fixed Over Current Protection、Over Temperature Protection、Enable、Short Circuit Protection Positive SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS.
PCBKit's library has its KiCad symbol (Pinmap_Generic:Regulator_Linear_1IN_2GND_3EN_4BYP_5OUT, from PCBKit's generic symbols) and its footprint (Package_TO_SOT_SMD:SOT-23-5, from KiCad's library), ready for a KiCad board. 110 are in stock at JLCPCB (part C129353).
Symbol
Footprint
From the datasheet
22- Supply, least
- 2.2 V · VIN, recommended operating minimum, legacy chip · p. 4
- Supply, most
- 16 V · VIN, recommended operating maximum, legacy chip · p. 4
- Supply, least
- 2.5 V · VIN, recommended operating minimum, new chip · p. 4
- Supply, absolute maximum
- 16 V · VIN, absolute maximum, legacy chip · p. 4
- Supply, absolute maximum
- 18 V · VIN, absolute maximum, new chip · p. 4
- Junction, hottest
- 125 °C · Operating junction temperature maximum · p. 4
- Gives
- 250 mA · Maximum recommended output current · p. 4
- Takes working
- 65 µA · Typical GND pin current, output enabled, IOUT = 0 mA, legacy chip · p. 6
- Takes working
- 69 µA · Typical GND pin current, output enabled, IOUT = 0 mA, new chip · p. 6
- Takes asleep
- 10 nA · Typical GND pin current, VON/OFF < 0.3 V, VIN = 16 V, legacy chip · p. 6
- Takes asleep
- 1.25 µA · Typical GND pin current, VON/OFF < 0.3 V, VIN = 16 V, new chip · p. 6
- Current limit
- 350 mA · Typical peak output current, VOUT ≥ VO(NOM) –5%, steady state, legacy chip · p. 7
- Dropout
- 450 mV · Typical dropout at IOUT = 250 mA, legacy chip · p. 7
- Dropout
- 225 mV · Typical dropout at IOUT = 250 mA, new chip · p. 7
- Junction to air (DBV (SOT23-5))
- 169.7 K/W · Junction-to-ambient thermal resistance, legacy chip · p. 5
- Junction to air (DBV (SOT23-5))
- 178.6 K/W · Junction-to-ambient thermal resistance, new chip · p. 5
- Junction to case (DBV (SOT23-5))
- 122.6 K/W · Junction-to-case top thermal resistance, legacy chip · p. 5
- Junction to case (DBV (SOT23-5))
- 77.9 K/W · Junction-to-case top thermal resistance, new chip · p. 5
- Junction to board (DBV (SOT23-5))
- 29.9 K/W · Junction-to-board thermal resistance, legacy chip · p. 5
- Junction to board (DBV (SOT23-5))
- 47.2 K/W · Junction-to-board thermal resistance, new chip · p. 5
- Works from
- -40 °C · minimum operating ambient temperature · p. 18
- Works up to
- 125 °C · maximum operating ambient temperature · p. 18
What it is and has
7- Output current
- Up to 250mA · p. 1
- Protection
- Output current limiting and thermal protection · p. 1
- Output capacitor compatibility
- Stable with 2.2µF ceramic capacitors · p. 1
- Output noise
- 30μVRMS with 10nF bypass capacitor · p. 1
- PSRR
- 70dB at 1kHz, 40dB at 1MHz · p. 1
- Package
- 5-pin SOT-23 (DBV) · p. 1
- Output accuracy
- ±1.5% for standard-grade legacy chip · p. 1
Around it
6- cap 1µF or larger
- between IN and GND; Input supply capacitor. · p. 3
- cap 2.2µF or larger
- between OUT and GND; Output capacitor; effective capacitance at the pin must remain greater than 1uF after derating. · p. 3
- cap 10nF
- between BYPASS and GND; Bypass capacitor for low noise performance. · p. 1
- cap 100nF
- between OUT and GND; New chip: low ESR MLCC close to the output pin when the output capacitor has higher ESR than 1Ω. · p. 4
- cap 10nF
- between BYPASS and GND; Optional bypass capacitor for low-noise operation; ceramic or film. · p. 23
- cap 4.7µF
- between OUT and GND; Minimum output capacitance for the legacy chip. Place within 1cm of the output pin and return to clean analog ground. · p. 23
Specifications
118| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Continuous input voltage range (for legacy chip) VIN | Legacy chip; voltages with respect to GND | min -0.3 · max 16 V | 4 |
| Continuous input voltage range (for new chip) VIN | New chip; voltages with respect to GND | min -0.3 · max 18 V | 4 |
| Output voltage range (for legacy chip) VOUT | Legacy chip | min -0.3 · max 9 V | 4 |
| Output voltage range (for new chip) VOUT | New chip; maximum is VIN + 0.3 or 9 (whichever is smaller) | min -0.3 V | 4 |
| BYPASS pin voltage range (for new chip) VBYPASS | New chip | min -0.3 · max 3 V | 4 |
| ON/OFF pin voltage range (for legacy chip) VON/OFF | Legacy chip | min -0.3 · max 16 V | 4 |
| ON/OFF pin voltage range (for new chip) VON/OFF | New chip | min -0.3 · max 18 V | 4 |
| Operating junction, TJ Temperature | min -55 · max 150 °C | 4 | |
| Storage, Tstg Temperature | min -65 · max 150 °C | 4 | |
| Electrostatic discharge V(ESD) | Legacy chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -2000 · max 2000 V | 4 |
| Electrostatic discharge V(ESD) | New chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -3000 · max 3000 V | 4 |
| Electrostatic discharge V(ESD) | Legacy chip; Charged device model (CDM), per JEDEC specification JESD22-C101 | min -500 · max 500 V | 4 |
| Electrostatic discharge V(ESD) | New chip; Charged device model (CDM), per JEDEC specification JESD22-C101 | min -1000 · max 1000 V | 4 |
| Supply input voltage (for legacy chip) VIN | Legacy chip | min 2.2 · max 16 V | 4 |
| Supply input voltage (for new chip) VIN | New chip | min 2.5 · max 16 V | 4 |
| Output voltage (for legacy chip) VOUT | Legacy chip | min 1.2 · max 10 V | 4 |
| Output voltage (for new chip) VOUT | New chip | min 1.2 · max 5 V | 4 |
| Bypass voltage VBYPASS | NOM column | typ 1.2 V | 4 |
| Enable voltage (for legacy chip) VON/OFF | Legacy chip; maximum VIN | min 0 V | 4 |
| Enable voltage (for new chip) VON/OFF | New chip | min 0 · max 16 V | 4 |
| Output current IOUT | min 0 · max 250 mA | 4 | |
| Input capacitor CIN | NOM column; capacitor values assumed to derate to 50% of nominal | typ 1 uF | 4 |
| Output capacitance (for legacy chip) COUT | Legacy chip; 4.7 is NOM | min 2.2 · typ 4.7 uF | 4 |
| Output capacitance (for new chip) (1) COUT | New chip; 2.2 is NOM; maintain effective output capacitance of 1 uF minimum | min 1 · typ 2.2 · max 200 uF | 4 |
| Output capacitor ESR (for new chip)(2) COUT ESR | New chip | min 0 · max 1 Ω | 4 |
| Operating junction temperature TJ | min -40 · max 125 °C | 4 | |
| Junction-to-ambient thermal resistance RθJA | Legacy chip; DBV (SOT23-5), 5 pins | typ 169.7 °C/W | 5 |
| Junction-to-ambient thermal resistance RθJA | New chip; DBV (SOT23-5), 5 pins | typ 178.6 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | Legacy chip; DBV (SOT23-5), 5 pins | typ 122.6 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | New chip; DBV (SOT23-5), 5 pins | typ 77.9 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | Legacy chip; DBV (SOT23-5), 5 pins | typ 29.9 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | New chip; DBV (SOT23-5), 5 pins | typ 47.2 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | Legacy chip; DBV (SOT23-5), 5 pins | typ 16.7 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | New chip; DBV (SOT23-5), 5 pins | typ 15.9 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | Legacy chip; DBV (SOT23-5), 5 pins | typ 29.4 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | New chip; DBV (SOT23-5), 5 pins | typ 46.9 °C/W | 5 |
| Output voltage tolerance ∆VOUT | Legacy chip (standard grade); IL = 1 mA | min -1.5 · max 1.5 % | 5 |
| Output voltage tolerance ∆VOUT | New chip; IL = 1 mA | min -0.5 · max 0.5 % | 5 |
| Output voltage tolerance ∆VOUT | Legacy chip (standard grade); 1 mA ≤ IL ≤ 50 mA | min -2.5 · max 2.5 % | 5 |
| Output voltage tolerance ∆VOUT | New chip; 1 mA ≤ IL ≤ 50 mA | min -0.5 · max 0.5 % | 5 |
| Output voltage tolerance ∆VOUT | Legacy chip (standard grade); 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C | min -3.5 · max 3.5 % | 5 |
| Output voltage tolerance ∆VOUT | New chip; 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C | min -1 · max 1 % | 5 |
| Output voltage tolerance ∆VOUT | Legacy chip (standard grade); 1 mA ≤ IL ≤ 250 mA | min -4 · max 4 % | 5 |
| Output voltage tolerance ∆VOUT | New chip; 1 mA ≤ IL ≤ 250 mA | min -0.5 · max 0.5 % | 5 |
| Output voltage tolerance ∆VOUT | Legacy chip (standard grade); 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C | min -5 · max 5 % | 5 |
| Output voltage tolerance ∆VOUT | New chip; 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C | min -1 · max 1 % | 5 |
| Line regulation ΔVOUT(ΔVIN) | Legacy chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V | typ 0.007 · max 0.014 %/V | 6 |
| Line regulation ΔVOUT(ΔVIN) | New chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V | typ 0.002 · max 0.014 %/V | 6 |
| Line regulation ΔVOUT(ΔVIN) | Legacy chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | typ 0.007 · max 0.032 %/V | 6 |
| Line regulation ΔVOUT(ΔVIN) | New chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | typ 0.002 · max 0.032 %/V | 6 |
| Minimum input voltage required to maintain output regulation VIN(MIN) | Legacy chip; TJ = 25°C | typ 2.05 V | 6 |
| Minimum input voltage required to maintain output regulation VIN(MIN) | New chip; TJ = 25°C | typ 2.05 V | 6 |
| Minimum input voltage required to maintain output regulation VIN(MIN) | Legacy chip; –40°C ≤ TJ ≤ 125°C | max 2.2 V | 6 |
| Minimum input voltage required to maintain output regulation VIN(MIN) | New chip; –40°C ≤ TJ ≤ 125°C | max 2.35 V | 6 |
| GND pin current IGND | Legacy chip; IOUT = 0 mA | typ 65 · max 95 uA | 6 |
| GND pin current IGND | New chip; IOUT = 0 mA | typ 69 · max 95 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C | max 125 uA | 6 |
| GND pin current IGND | New chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C | max 123 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 1 mA | typ 75 · max 110 uA | 6 |
| GND pin current IGND | New chip; IOUT = 1 mA | typ 78 · max 110 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C | max 170 uA | 6 |
| GND pin current IGND | New chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C | max 140 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 50 mA | typ 350 · max 600 uA | 6 |
| GND pin current IGND | New chip; IOUT = 50 mA | typ 380 · max 440 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C | max 1000 uA | 6 |
| GND pin current IGND | New chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C | max 650 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 150 mA | typ 850 · max 1500 uA | 6 |
| GND pin current IGND | New chip; IOUT = 150 mA | typ 765 · max 890 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C | max 2500 uA | 6 |
| GND pin current IGND | New chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C | max 1060 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 250 mA | typ 1500 · max 2300 uA | 6 |
| GND pin current IGND | New chip; IOUT = 250 mA | typ 875 · max 1010 uA | 6 |
| GND pin current IGND | Legacy chip; IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C | max 4000 uA | 6 |
| GND pin current IGND | New chip; IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C | max 1200 uA | 6 |
| GND pin current IGND | Legacy chip; VON/OFF < 0.3 V, VIN = 16 V | typ 0.01 · max 0.8 uA | 6 |
| GND pin current IGND | New chip; VON/OFF < 0.3 V, VIN = 16 V | typ 1.25 · max 1.75 uA | 6 |
| GND pin current IGND | Legacy chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C | typ 0.05 · max 2 uA | 6 |
| GND pin current IGND | New chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C | typ 1.12 · max 2.75 uA | 6 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 0 mA | typ 0.5 · max 2.5 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 0 mA | typ 1 · max 2.75 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C | max 4 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C | max 3 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 1 mA | typ 5 · max 9 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 1 mA | typ 11.5 · max 14 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C | max 12 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C | max 17 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 50 mA | typ 100 · max 125 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 50 mA | typ 120 · max 145 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C | max 180 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C | max 184 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 150 mA | typ 260 · max 325 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 150 mA | typ 180 · max 198 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C | max 470 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C | max 254 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 250 mA | typ 450 · max 575 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 250 mA | typ 225 · max 260 mV | 7 |
| Dropout voltage(1) VDO | Legacy chip; IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C | max 850 mV | 7 |
| Dropout voltage(1) VDO | New chip; IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C | max 340 mV | 7 |
| ON/OFF input voltage VON/OFF | Legacy chip; Low = Output OFF | typ 0.55 V | 7 |
| ON/OFF input voltage VON/OFF | New chip; Low = Output OFF | typ 0.72 V | 7 |
| ON/OFF input voltage VON/OFF | Legacy chip; Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | max 0.15 V | 7 |
| ON/OFF input voltage VON/OFF | New chip; Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | max 0.15 V | 7 |
| ON/OFF input voltage VON/OFF | Legacy chip; High = Output ON | typ 1.4 V | 7 |
| ON/OFF input voltage VON/OFF | New chip; High = Output ON | typ 0.85 V | 7 |
| ON/OFF input voltage VON/OFF | Legacy chip; High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | min 1.6 V | 7 |
| ON/OFF input voltage VON/OFF | New chip; High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | min 1.6 V | 7 |
| ON/OFF input current ION/OFF | Legacy chip; VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | max -2 uA | 7 |
| ON/OFF input current ION/OFF | New chip; VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | max -0.9 uA | 7 |
| ON/OFF input current ION/OFF | Legacy chip; VON/OFF = 0 V | typ 0.01 uA | 7 |
| ON/OFF input current ION/OFF | New chip; VON/OFF = 0 V | typ 0.42 uA | 7 |
| Peak output current IO(PK) | Legacy chip; VOUT ≥ VO(NOM) –5% (steady state) | min 300 · typ 350 mA | 7 |
| Peak output current IO(PK) | New chip; VOUT ≥ VO(NOM) –5% (steady state) | min 300 · typ 350 mA | 7 |
| Short output current IO(SC) | Legacy chip; RL = 0 Ω (steady state) | typ 400 mA | 7 |
| Short output current IO(SC) | New chip; RL = 0 Ω (steady state) | typ 375 mA | 7 |
| Ripple rejection ΔVO/ΔVIN | Legacy chip; f = 1 kHz, CBYPASS = 10 nF, COUT = 10 uF | typ 45 dB | 7 |
| Ripple rejection ΔVO/ΔVIN | New chip; f = 1 kHz, CBYPASS = 10 nF, COUT = 10 uF | typ 78 dB | 7 |
| Output noise voltage Vn | Legacy chip; Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 uF, VOUT = 3.3 V | typ 30 uVRMS | 7 |
| Output noise voltage Vn | New chip; Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 uF, VOUT = 3.3 V | typ 30 uVRMS | 7 |
Pins, by the datasheet
5- 1 IN
- Input supply; connect a capacitor of 1uF or larger to ground. · p. 3
- 2 GND
- Ground. · p. 3
- 3 ON/OFF
- High enables the regulator; low disables it. Tie to VIN if unused. · p. 3
- 4 BYPASS
- Connect an external capacitor to ground to reduce reference voltage noise. · p. 3
- 5 OUT
- Regulator output; connect a capacitor of 2.2uF or larger to ground, maintaining effective capacitance greater than 1uF. · p. 3
Parameters
18- Current Limit
- 350mA
- Features
- Noise bypass terminal
- Junction Temperature(Max)
- 125℃
- Noise
- 30uVrms
- Number of Outputs
- 1
- Operating Temperature
- -40℃~+125℃
- Output Configuration
- Positive
- Output Current
- 250mA
- Output Type
- Fixed
- Output Voltage
- 3.3V
- Power Supply Rejection Ratio (PSRR)
- 45dB@(1kHz)
- Thermal Resistance(Junction to Ambient)
- 178.6℃/W
- Thermal Resistance(Junction to Board)
- 47.2℃/W
- Thermal Resistance(Junction to Case)
- 122.6℃/W
- Voltage - Supply
- 2.2V~16V
- Voltage - Supply(Absolute Max)
- 16V
- Voltage Dropout
- 850mV@(250mA)
- standby current
- 800nA
Order codes
2- LP2992IM5-3.3/NOPBLCSC C129353
- LP2992IM5-3.3LCSC C3751592
Pinout
5| Pin | Name | Type |
|---|---|---|
| 1 | IN | Power in |
| 2 | GND | Power in |
| 3 | EN | Input |
| 4 | BYP | Passive |
| 5 | OUT | Power out |
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Is there a KiCad symbol and footprint for the LP2992IM5-3.3?
Yes. The symbol is Pinmap_Generic:Regulator_Linear_1IN_2GND_3EN_4BYP_5OUT and the footprint Package_TO_SOT_SMD:SOT-23-5, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the LP2992IM5-3.3?
SOT-23-5, with 5 pins. Its footprint is drawn on this page.
Where is the LP2992IM5-3.3 datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the LP2992IM5-3.3?
JLCPCB lists it as part C129353, with 110 in stock; the sellers' links on this page open their listings.
What can replace the LP2992IM5-3.3?
Parts like it in the library: the ME6211C33M5G-N by MICRONE, the SPX3819M5-L-3-3/TR by MaxLinear, the RT9013-33GB by RICHTEK and the XC6219B332MR by UMW. Check their datasheets: a part that fits the footprint may still differ in its ratings.
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