LP2985-33DBV

Q: Is there a KiCad symbol and footprint for the LP2985-33DBV?

Yes. The symbol is dk_PMIC-Voltage-Regulators-Linear:LP2985-33DBVR and the footprint Package_TO_SOT_SMD:SOT-23-5, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the LP2985-33DBV?

SOT-23-5, with 5 pins. Its footprint is drawn on this page.

Q: Where is the LP2985-33DBV datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the LP2985-33DBV?

JLCPCB lists it as part C95414, with 135,106 in stock; the sellers' links on this page open their listings.

Q: What can replace the LP2985-33DBV?

Parts like it in the library: the ME6211C33M5G-N by MICRONE, the SPX3819M5-L-3-3/TR by MaxLinear, the RT9013-33GB by RICHTEK and the XC6219B332MR by UMW. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the LP2985-33DBV?

152 boards in 133 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

Texas InstrumentsExtended

-40℃~+125℃@(Tj) 1 150mA 16V 3.3V 30uVrms 45dB@(1kHz) 575mV@(150mA) 850uA Fixed Over Current Protection、Short Circuit Protection、Thermal shutdown、Enable control、Noise bypass terminal Positive SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS

Datasheet JLCPCB LCSC

Part id: ti/LP2985-33DBV
Category: Voltage Regulators, Linear, Low Drop Out (LDO) Regulators
Package: SOT-23-5
Pins: 5
In stock: 135,106 at JLCPCB (C95414)
Used on: 152 open-source boards

Overview

The LP2985-33DBV is a voltage Regulators, Linear, Low Drop Out (LDO) Regulator made by Texas Instruments in a SOT-23-5 package with 5 pins. -40℃~+125℃@(Tj) 1 150mA 16V 3.3V 30uVrms 45dB@(1kHz) 575mV@(150mA) 850uA Fixed Over Current Protection、Short Circuit Protection、Thermal shutdown、Enable control、Noise bypass terminal Positive SOT-23-5 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS.

PCBKit's library has its KiCad symbol (dk_PMIC-Voltage-Regulators-Linear:LP2985-33DBVR, from Digikey) and its footprint (Package_TO_SOT_SMD:SOT-23-5, from KiCad's library), ready for a KiCad board. 135,106 are in stock at JLCPCB (part C95414). 152 open-source boards in 133 repositories on GitHub use it.

Symbol

dk_PMIC-Voltage-Regulators-Linear:LP2985-33DBVRFrom Digikey

Footprint

Package_TO_SOT_SMD:SOT-23-5From KiCad's library

From the datasheet

Supply, least: 2.2 V · VIN, recommended operating min, legacy chip · p. 4
Supply, most: 16 V · VIN, recommended operating max, legacy chip · p. 4
Supply, least: 2.5 V · VIN, recommended operating min, new chip · p. 4
Supply, absolute maximum: 16 V · VIN, absolute max, legacy chip · p. 4
Supply, absolute maximum: 18 V · VIN, absolute max, new chip · p. 4
Junction, hottest: 150 °C · Operating junction, absolute max · p. 4
Gives: 150 mA · IOUT, recommended continuous max · p. 4
Takes working: 65 µA · GND pin current typical, IOUT = 0 mA, legacy chip · p. 7
Takes working: 69 µA · GND pin current typical, IOUT = 0 mA, new chip · p. 7
Takes asleep: 10 nA · GND pin current typical, VON/OFF < 0.3 V, VIN = 16 V, legacy chip · p. 7
Takes asleep: 1.25 µA · GND pin current typical, VON/OFF < 0.3 V, VIN = 16 V, new chip · p. 7
Current limit: 350 mA · Peak Output Current typical, VOUT ≥ VO(NOM) –5%, steady state, legacy chip · p. 8
Dropout: 280 mV · Dropout typical at IOUT = 150 mA, legacy chip · p. 6
Dropout: 180 mV · Dropout typical at IOUT = 150 mA, new chip · p. 6
Junction to air (DBV (SOT23-5)): 205.4 K/W · Junction-to-ambient, legacy chip · p. 5
Junction to air (DBV (SOT23-5)): 178.6 K/W · Junction-to-ambient, new chip · p. 5
Junction to case (DBV (SOT23-5)): 78.8 K/W · Junction-to-case top, legacy chip · p. 5
Junction to case (DBV (SOT23-5)): 77.9 K/W · Junction-to-case top, new chip · p. 5
Junction to board (DBV (SOT23-5)): 46.7 K/W · Junction-to-board, legacy chip · p. 5
Junction to board (DBV (SOT23-5)): 47.2 K/W · Junction-to-board, new chip · p. 5

What it is and has

Output current: Up to 150mA · p. 1
Output accuracy: ±1.5%, standard-grade legacy chip · p. 1
Output accuracy: ±0.5%, new chip only · p. 1
Output noise: 30μVRMS with 10nF bypass capacitor · p. 1
Protection: Output current limiting and thermal protection · p. 1
Output capacitor: Stable with 2.2µF ceramic capacitor · p. 1
Package: 5-pin SOT-23 (DBV) · p. 1
Operating junction temperature: –40°C to +125°C · p. 1

Around it

cap 1 µF or larger: between VIN and GND; Input capacitor. · p. 3
cap 2.2 µF or larger: between VOUT and GND; Output capacitor; effective capacitance at the pin must be greater than 1 uF. · p. 3
cap 10 nF: between BYPASS and GND; Bypass capacitor used for the stated output-noise performance. · p. 8

Specifications

124

Parameter	Conditions	As printed	Page
Continuous input voltage range (for legacy chip) VIN	Legacy chip	min -0.3 · max 16 V	4
Continuous input voltage range (for new chip) VIN	New chip	min -0.3 · max 18 V	4
Output voltage range (for legacy chip) VOUT	Legacy chip	min -0.3 · max 9 V	4
Output voltage range (for new chip) VOUT	New chip; maximum is VIN + 0.3 V or 9 V, whichever is smaller	min -0.3 V	4
BYPASS pin voltage range (for new chip) VBYPASS	New chip	min -0.3 · max 3 V	4
ON/OFF pin voltage range (for legacy chip) VON/OFF	Legacy chip	min -0.3 · max 16 V	4
ON/OFF pin voltage range (for new chip) VON/OFF	New chip	min -0.3 · max 18 V	4
Operating junction, TJ Temperature		min -55 · max 150 °C	4
Storage, Tstg Temperature		min -65 · max 150 °C	4
Electrostatic discharge V(ESD)	Legacy chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001	min -2000 · max 2000 V	4
Electrostatic discharge V(ESD)	New chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001	min -3000 · max 3000 V	4
Electrostatic discharge V(ESD)	Legacy chip; Charged device model (CDM), per JEDEC specification JESD22-C101	min -500 · max 500 V	4
Electrostatic discharge V(ESD)	New chip; Charged device model (CDM), per JEDEC specification JESD22-C101	min -1000 · max 1000 V	4
Supply input voltage (for legacy chip) VIN	Legacy chip	min 2.2 · max 16 V	4
Supply input voltage (for new chip) VIN	New chip	min 2.5 · max 16 V	4
Output voltage (for legacy chip) VOUT	Legacy chip	min 1.2 · max 10 V	4
Output voltage (for new chip) VOUT	New chip	min 1.2 · max 5 V	4
Bypass voltage VBYPASS	NOM column	typ 1.2 V	4
Enable voltage (for legacy chip) VON/OFF	Legacy chip; maximum VIN	min 0 V	4
Enable voltage (for new chip) VON/OFF	New chip	min 0 · max 16 V	4
Output current IOUT		min 0 · max 150 mA	4
Input capacitor CIN	NOM column; capacitor values assumed to derate to 50% of nominal	typ 1 uF	4
Output capacitor (for legacy chip) COUT	Legacy chip; nominal value in typ	min 2.2 · typ 4.7 uF	4
Output capacitance (for new chip) COUT	New chip; nominal value in typ; maintain effective output capacitance of 1 uF minimum	min 1 · typ 2.2 · max 200 uF	4
Operating junction temperature TJ		min -40 · max 125 °C	4
Junction-to-ambient thermal resistance RθJA	Legacy chip; DBV (SOT23-5), 5 PINS	typ 205.4 °C/W	5
Junction-to-ambient thermal resistance RθJA	New chip; DBV (SOT23-5), 5 PINS	typ 178.6 °C/W	5
Junction-to-case (top) thermal resistance RθJC(top)	Legacy chip; DBV (SOT23-5), 5 PINS	typ 78.8 °C/W	5
Junction-to-case (top) thermal resistance RθJC(top)	New chip; DBV (SOT23-5), 5 PINS	typ 77.9 °C/W	5
Junction-to-board thermal resistance RθJB	Legacy chip; DBV (SOT23-5), 5 PINS	typ 46.7 °C/W	5
Junction-to-board thermal resistance RθJB	New chip; DBV (SOT23-5), 5 PINS	typ 47.2 °C/W	5
Junction-to-top characterization parameter ψJT	Legacy chip; DBV (SOT23-5), 5 PINS	typ 8.3 °C/W	5
Junction-to-top characterization parameter ψJT	New chip; DBV (SOT23-5), 5 PINS	typ 15.9 °C/W	5
Junction-to-board characterization parameter ψJB	Legacy chip; DBV (SOT23-5), 5 PINS	typ 46.3 °C/W	5
Junction-to-board characterization parameter ψJB	New chip; DBV (SOT23-5), 5 PINS	typ 46.9 °C/W	5
Output voltage tolerance ∆VOUT	Legacy chip (standard grade); IL = 1 mA	min -1.5 · max 1.5 %	5
Output voltage tolerance ∆VOUT	New chip; IL = 1 mA	min -0.5 · max 0.5 %	5
Output voltage tolerance ∆VOUT	Legacy chip (standard grade); 1 mA ≤ IL ≤ 50 mA	min -2.5 · max 2.5 %	5
Output voltage tolerance ∆VOUT	New chip; 1 mA ≤ IL ≤ 50 mA	min -0.5 · max 0.5 %	5
Output voltage tolerance ∆VOUT	Legacy chip (standard grade); 1 mA ≤ IL ≤ 150 mA	min -3 · max 3 %	5
Output voltage tolerance ∆VOUT	New chip; 1 mA ≤ IL ≤ 150 mA	min -0.5 · max 0.5 %	5
Output voltage tolerance ∆VOUT	Legacy chip (standard grade); 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C	min -3.5 · max 3.5 %	5
Output voltage tolerance ∆VOUT	New chip; 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C	min -1 · max 1 %	5
Output voltage tolerance ∆VOUT	Legacy chip (standard grade); 1 mA ≤ IL ≤ 150 mA, –40°C ≤ TJ ≤ 125°C	min -4 · max 4 %	5
Output voltage tolerance ∆VOUT	New chip; 1 mA ≤ IL ≤ 150 mA, –40°C ≤ TJ ≤ 125°C	min -1 · max 1 %	5
Line Regulation ΔVOUT(ΔVIN)	Legacy chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V	typ 0.007 · max 0.014 %/V	5
Line Regulation ΔVOUT(ΔVIN)	New chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V	typ 0.002 · max 0.014 %/V	5
Line Regulation ΔVOUT(ΔVIN)	Legacy chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	typ 0.007 · max 0.032 %/V	5
Line Regulation ΔVOUT(ΔVIN)	New chip; VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	typ 0.002 · max 0.032 %/V	5
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 0 mA	typ 1 · max 3 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 0 mA	typ 1 · max 2.75 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C	max 5 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C	max 3 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 1 mA	typ 7 · max 10 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 1 mA	typ 11.5 · max 14 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C	max 15 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C	max 17 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 10 mA	typ 40 · max 60 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 10 mA	typ 98 · max 115 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C	max 90 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C	max 148 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 50 mA	typ 120 · max 150 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 50 mA	typ 120 · max 145 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C	max 225 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C	max 184 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 150 mA	typ 280 · max 350 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 150 mA	typ 180 · max 198 mV	6
Dropout voltage VIN - VOUT	Legacy chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C	max 575 mV	6
Dropout voltage VIN - VOUT	New chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C	max 254 mV	6
GND pin current IGND	Legacy chip; IOUT = 0 mA	typ 65 · max 95 uA	7
GND pin current IGND	New chip; IOUT = 0 mA	typ 69 · max 95 uA	7
GND pin current IGND	Legacy chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C	max 125 uA	7
GND pin current IGND	New chip; IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C	max 120 uA	7
GND pin current IGND	Legacy chip; IOUT = 1 mA	typ 75 · max 110 uA	7
GND pin current IGND	New chip; IOUT = 1 mA	typ 78 · max 105 uA	7
GND pin current IGND	Legacy chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C	max 170 uA	7
GND pin current IGND	New chip; IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C	max 130 uA	7
GND pin current IGND	Legacy chip; IOUT = 10 mA	typ 120 · max 220 uA	7
GND pin current IGND	New chip; IOUT = 10 mA	typ 175 · max 200 uA	7
GND pin current IGND	Legacy chip; IOUT = 1 0mA, –40°C ≤ TJ ≤ 125°C	max 400 uA	7
GND pin current IGND	New chip; IOUT = 1 0mA, –40°C ≤ TJ ≤ 125°C	max 240 uA	7
GND pin current IGND	Legacy chip; IOUT = 50 mA	typ 350 · max 600 uA	7
GND pin current IGND	New chip; IOUT = 50 mA	typ 380 · max 410 uA	7
GND pin current IGND	Legacy chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C	max 900 uA	7
GND pin current IGND	New chip; IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C	max 590 uA	7
GND pin current IGND	Legacy chip; IOUT = 150 mA	typ 850 · max 1200 uA	7
GND pin current IGND	New chip; IOUT = 150 mA	typ 765 · max 890 uA	7
GND pin current IGND	Legacy chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C	max 2000 uA	7
GND pin current IGND	New chip; IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C	max 1060 uA	7
GND pin current IGND	Legacy chip; VON/OFF < 0.3 V, VIN = 16 V	typ 0.01 · max 0.08 uA	7
GND pin current IGND	New chip; VON/OFF < 0.3 V, VIN = 16 V	typ 1.25 · max 1.75 uA	7
GND pin current IGND	Legacy chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C	typ 0 · max 1 uA	7
GND pin current IGND	New chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C	typ 1.12 · max 2.25 uA	7
GND pin current IGND	Legacy chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C	typ 0.01 · max 2 uA	7
GND pin current IGND	New chip; VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C	typ 1.12 · max 2.75 uA	7
Rising bias supply UVLO VUVLO+	New chip; VIN rising, –40°C ≤ TJ ≤ 125°C	typ 2.2 · max 2.4 V	7
Falling bias supply UVLO VUVLO-	New chip; VIN falling, –40°C ≤ TJ ≤ 125°C	min 1.9 V	7
UVLO hysteresis VUVLO(HYST)	New chip; –40°C ≤ TJ ≤ 125°C	typ 0.13 V	7
ON/OFF input voltage VON/OFF	Legacy chip; Low = O/P OFF	typ 0.55 V	7
ON/OFF input voltage VON/OFF	New chip; Low = O/P OFF	typ 0.72 V	7
ON/OFF input voltage VON/OFF	Legacy chip; Low = O/P OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	max 0.15 V	7
ON/OFF input voltage VON/OFF	New chip; Low = O/P OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	max 0.15 V	7
ON/OFF input voltage VON/OFF	Legacy chip; High = O/P ON	typ 1.4 V	7
ON/OFF input voltage VON/OFF	New chip; High = O/P ON	typ 0.85 V	7
ON/OFF input voltage VON/OFF	Legacy chip; High = O/P ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	min 1.6 V	7
ON/OFF input voltage VON/OFF	New chip; High = O/P ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	min 1.6 V	7
ON/OFF input current ION/OFF	Legacy chip; VON/OFF = 0 V	typ 0.01 uA	8
ON/OFF input current ION/OFF	New chip; VON/OFF = 0 V	typ 0.42 uA	8
ON/OFF input current ION/OFF	Legacy chip; VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V,–40°C ≤ TJ ≤ 125°C	max -1 uA	8
ON/OFF input current ION/OFF	New chip; VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V,–40°C ≤ TJ ≤ 125°C	max -0.9 uA	8
ON/OFF input current ION/OFF	Legacy chip; VON/OFF = 5 V	typ 5 uA	8
ON/OFF input current ION/OFF	New chip; VON/OFF = 5 V	typ 0.011 uA	8
ON/OFF input current ION/OFF	Legacy chip; VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	max 15 uA	8
ON/OFF input current ION/OFF	New chip; VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C	max 2.2 uA	8
Peak Output Current IO(PK)	Legacy chip; VOUT ≥ VO(NOM) –5% (steady state)	min 300 · typ 350 mA	8
Peak Output Current IO(PK)	New chip; VOUT ≥ VO(NOM) –5% (steady state)	min 300 · typ 350 mA	8
Short Output Current IO(SC)	Legacy chip; RL = 0 Ω (steady state)	typ 400 mA	8
Short Output Current IO(SC)	New chip; RL = 0 Ω (steady state)	typ 375 mA	8
Ripple Rejection ΔVO/ΔVIN	Legacy chip; f = 1 kHz, CBYPASS = 10 nF, COUT = 10 uF	typ 45 dB	8
Ripple Rejection ΔVO/ΔVIN	New chip; f = 1 kHz, CBYPASS = 10 nF, COUT = 10 uF	typ 78 dB	8
Output noise voltage Vn	Legacy chip; Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 uF, VOUT = 3.3V, ILOAD = 150 mA	typ 30 uVRMS	8
Output noise voltage Vn	New chip; Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 uF, VOUT = 3.3V, ILOAD = 150 mA	typ 30 uVRMS	8
Thermal shutdown threshold Tsd+	New chip; Shutdown, temperature increasing	typ 170 °C	8
Thermal shutdown threshold Tsd-	New chip; Reset, temperature decreasing	typ 150 °C	8

Pins, by the datasheet

1 VIN: Input supply; connect a capacitor of 1 uF or larger to ground. · p. 3
2 GND: Ground. · p. 3
3 ON/OFF: High enables the LDO; low disables it. Tie to VIN if unused. · p. 3
4 BYPASS: Connect an external capacitor to ground to reduce reference voltage noise. · p. 3
5 VOUT: Regulator output; connect a capacitor of 2.2 uF or larger to ground, maintaining effective capacitance greater than 1 uF. · p. 3

Parameters

Current Limit: 350mA
Dropout Voltage: 575mV@(150mA)
Features: Noise bypass terminal
Junction Temperature(Max): 150℃
Maximum Input Voltage: 16V
Noise: 30uVrms
Number of Outputs: 1
Operating Temperature: -40℃~+125℃@(Tj)
Output Configuration: Positive
Output Current: 150mA
Output Polarity: Positive
Output Type: Fixed
Output Voltage: 3.3V
Power Supply Rejection Ratio (PSRR): 45dB@(1kHz)
Thermal Resistance(Junction to Ambient): 205.4℃/W
Thermal Resistance(Junction to Board): 47.2℃/W
Thermal Resistance(Junction to Case): 78.8℃/W
Voltage - Supply: 2.2V~16V
Voltage - Supply(Absolute Max): 16V
Voltage Dropout: 280mV@(150mA)
standby current: 850uA

Order codes

LP2985-33DBVTG4LCSC C2865052
LP2985-33DBVRG4LCSC C2868561
LP2985-33DBVTLCSC C75216
LP2985-33DBVRLCSC C95414

Pinout

The pins of the LP2985-33DBV
Pin	Name	Type
1	VIN	Power in
2	GND	Power in
3	ON/OFF	Input
4	BYP	Passive
5	VOUT	Power out

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Parts like it

Questions

Is there a KiCad symbol and footprint for the LP2985-33DBV?

Yes. The symbol is dk_PMIC-Voltage-Regulators-Linear:LP2985-33DBVR and the footprint Package_TO_SOT_SMD:SOT-23-5, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the LP2985-33DBV?

SOT-23-5, with 5 pins. Its footprint is drawn on this page.

Where is the LP2985-33DBV datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the LP2985-33DBV?

JLCPCB lists it as part C95414, with 135,106 in stock; the sellers' links on this page open their listings.

What can replace the LP2985-33DBV?

Parts like it in the library: the ME6211C33M5G-N by MICRONE, the SPX3819M5-L-3-3/TR by MaxLinear, the RT9013-33GB by RICHTEK and the XC6219B332MR by UMW. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the LP2985-33DBV?

152 boards in 133 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

LP2985-33DBV

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

OpenThereminV45

Foc driver

Z80vga

JTAGProgrammer

Up5k osc

Si5351ABreakout panel

RP2040 Audio

DWAVE

Parts like it

ME6211C33M5G-N

SPX3819M5-L-3-3/TR

RT9013-33GB

XC6219B332MR

TPS7A2033PDBV

TPLP5907MFX-3.3

STLQ015M33R

RT9078-33GJ5