4 layers85 × 50 mm
Overview
The ISO1640BD is an I2C Isolator made by Texas Instruments in a SOIC-8 package with 8 pins. Bidirectional automatic direction、Open-drain buffer output、Hotswap SOIC-8 I2C Isolators ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:ISO1640BDR, from EasyEDA) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 4,848 are in stock at JLCPCB (part C5122339). 6 open-source boards in 5 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
16- Supply, least
- 3 V · VCC1, recommended operating min · p. 6
- Supply, most
- 5.5 V · VCC1, recommended operating max · p. 6
- Supply, least
- 2.25 V · VCC2, recommended operating min · p. 6
- Supply, absolute maximum
- 6 V · VCC1 and VCC2, absolute max · p. 6
- Works from
- -40 °C · Ambient temperature min · p. 7
- Works up to
- 125 °C · Ambient temperature max · p. 7
- Junction, hottest
- 150 °C · Junction temperature absolute max · p. 6
- A pin gives at most
- 20 mA · SDA1 or SCL1, absolute max · p. 6
- A pin gives at most
- 100 mA · SDA2 or SCL2, absolute max · p. 6
- Junction to air (D (SOIC))
- 106.3 K/W · Junction-to-ambient thermal resistance · p. 7
- Junction to case (D (SOIC))
- 38.5 K/W · Junction-to-case (top) thermal resistance · p. 7
- Junction to board (D (SOIC))
- 52.5 K/W · Junction-to-board thermal resistance · p. 7
- Takes working
- 10.3 mA · sum of ICC1 and ICC2 typical, 4.5–5.5 V, SDA and SCL low, unloaded · p. 14
- Takes at most
- 14 mA · sum of ICC1 and ICC2 max, 4.5–5.5 V, SDA and SCL low, unloaded · p. 14
- Edge
- 16 ns · typical SDA1/SCL1 fall time, 4.5–5.5 V, C1 = 40 pF, 70% to 30% · p. 16
- Data rate, most
- 1.7 Mbit/s · max ISO164x signaling rate, fast mode plus · p. 28
What it is and has
8- Isolated I2C channels
- Bidirectional SDA and SCL · p. 1
- Hot swap
- SDA and SCL · p. 1
- Bidirectional data transfer frequency
- Up to 1.7 MHz · p. 1
- Common-mode transient immunity
- ±100 kV/μs typical · p. 1
- Isolated channels
- Bidirectional SDA and SCL · p. 1
- Maximum operating frequency
- 1.7 MHz · p. 1
- I2C
- Isolated bidirectional SDA and SCL · p. 1
- Operating frequency
- Up to 1.7 MHz · p. 1
Around it
1- cap 0.1 µF
- between VCC1 and GND1; Decoupling capacitor; place as close as possible, within 2 mm of the supply pin. · p. 30
Specifications
108| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply Voltage | VCC1, VCC2; over operating free-air temperature range | min -0.5 · max 6 V | 6 |
| Input/Output Voltage | SDA1, SCL1; over operating free-air temperature range | min -0.5 V | 6 |
| Input/Output Voltage | SDA2, SCL2; over operating free-air temperature range | min -0.5 V | 6 |
| Input/Output Current | SDA1, SCL1; over operating free-air temperature range | min 0 · max 20 mA | 6 |
| Input/Output Current | SDA2, SCL2; over operating free-air temperature range | min 0 · max 100 mA | 6 |
| Maximum junction temperature TJ | max 150 °C | 6 | |
| Storage temperature Tstg | min -65 · max 150 °C | 6 | |
| Electrostatic discharge V(ESD) | All pins; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -6000 · max 6000 V | 6 |
| Electrostatic discharge V(ESD) | ISO1640/1: Bus pins (SDA1, SCL1); Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -10000 · max 10000 V | 6 |
| Electrostatic discharge V(ESD) | ISO1640/1: Bus pins (SDA2, SCL2); Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 | min -14000 · max 14000 V | 6 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per JEDEC specification JESD22-C101 | min -1500 · max 1500 V | 6 |
| Electrostatic discharge V(ESD) | Contact discharge per IEC 61000-4-2; Isolation barrier withstand test | min -8000 · max 8000 V | 6 |
| Electrostatic discharge V(ESD) | ISO1640/1: SCL2, SDA2; Same side unpowered IEC ESD contact discharge per IEC 61000-4-2; Side 2 | min -8000 · max 8000 V | 6 |
| UVLO threshold when supply voltage is rising on Side 1 VCC1(UVLO+) | typ 2.7 · max 2.9 V | 6 | |
| UVLO threshold when supply voltage is falling on Side 1 VCC1(UVLO-) | min 2.3 · typ 2.6 V | 6 | |
| UVLO threshold when supply voltage is rising on Side 2 VCC2(UVLO+) | typ 2 · max 2.25 V | 6 | |
| UVLO threshold when supply voltage is falling on Side 2 VCC2(UVLO-) | min 1.7 · typ 1.8 V | 6 | |
| Supply voltage UVLO hysteresis, Side 1 VHYS1(UVLO) | min 100 · typ 150 mV | 6 | |
| Supply voltage UVLO hysteresis, Side 2 VHYS2(UVLO) | min 100 · typ 150 mV | 6 | |
| Supply voltage, Side 1 VCC1 | min 3 · max 5.5 V | 6 | |
| Supply voltage, Side 2 VCC2 | min 2.25 · max 5.5 V | 6 | |
| I2C Input and output signal voltages, Side 1 VSDA1, VSCL1 | min 0 V | 6 | |
| I2C Input and output signal voltages, Side 2 VSDA2, VSCL2 | min 0 V | 7 | |
| I2C Low-level input voltage, Side 1 VIL1 | min 0 · max 480 mV | 7 | |
| I2C Low-level input voltage, Side 2 VIL2 | min 0 V | 7 | |
| I2C Output current, Side 1 IOL1 | min 0.5 · max 3.5 mA | 7 | |
| I2C Output current, Side 2 IOL2 | min 0.5 · max 50 mA | 7 | |
| Capacitive load, Side 1 C1 | max 80 pF | 7 | |
| Capacitive load, Side 2 C2 | max 400 pF | 7 | |
| I2C Operating frequency fMAX | Maximum frequency is a function of the RC time constant on the bus | max 1.7 MHz | 7 |
| Ambient temperature TA | min -40 · typ 25 · max 125 °C | 7 | |
| Junction-to-ambient thermal resistance RθJA | ISO1640/1; D (SOIC), 8 PINS | typ 106.3 °C/W | 7 |
| Junction-to-case (top) thermal resistance RθJC(top) | ISO1640/1; D (SOIC), 8 PINS | typ 38.5 °C/W | 7 |
| Junction-to-board thermal resistance RθJB | ISO1640/1; D (SOIC), 8 PINS | typ 52.5 °C/W | 7 |
| Junction-to-top characterization parameter ψJT | ISO1640/1; D (SOIC), 8 PINS | typ 8.2 °C/W | 7 |
| Junction-to-board characterization parameter ψJB | ISO1640/1; D (SOIC), 8 PINS | typ 51.8 °C/W | 7 |
| Maximum power dissipation (both sides) PD | ISO1640; VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | max 96 mW | 7 |
| Maximum power dissipation (side-1) PD1 | ISO1640; VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | max 43 mW | 7 |
| Maximum power dissipation (side-2) PD2 | ISO1640; VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal | max 53 mW | 7 |
| External clearance CLR | D; IEC 60664-1; Side 1 to side 2 distance through air | min 4 mm | 9 |
| External Creepage CPG | D; IEC 60664-1; Side 1 to side 2 distance across package surface | min 4 mm | 9 |
| Distance through the insulation DTI | D; Minimum internal gap (internal clearance); specification >17 um | min 17 um | 9 |
| Comparative tracking index CTI | D; IEC 60112; UL 746A; specification >400 V | min 400 V | 9 |
| Maximum repetitive peak isolation voltage VIORM | D; DIN V VDE V 0884-11:2017-01; AC voltage (bipolar) | max 637 VPK | 9 |
| Maximum isolation working voltage VIOWM | D; AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test | max 450 VRMS | 9 |
| Maximum isolation working voltage VIOWM | D; DC voltage | max 637 VDC | 9 |
| Maximum transient isolation voltage VIOTM | D; VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) | max 4242 VPK | 9 |
| Maximum surge isolation voltage VIOSM | D; Test method per IEC 62368-1, 1.2/50 us waveform, VTEST = 1.3 × VIOSM = 6,500 VPK (Basic qualification) | max 5000 VPK | 9 |
| Apparent charge qpd | D; Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge qpd | D; Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge qpd | D; Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm = 1 s | max 5 pC | 9 |
| Barrier capacitance, input to output CIO | D; VIO = 0.4 × sin (2 πft), f = 1 MHz | typ 1 pF | 9 |
| Withstand isolation voltage VISO | D; UL 1577; VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) | max 3000 VRMS | 9 |
| Safety input, output, or supply current IS | ISO1640/1 D-8 PACKAGE; RθJA = 106.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | max 214 mA | 11 |
| Safety input, output, or supply current IS | ISO1640/1 D-8 PACKAGE; RθJA = 106.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | max 327 mA | 11 |
| Safety input, output, or total power PS | ISO1640/1 D-8 PACKAGE; RθJA = 106.3 °C/W, TJ = 150°C, TA = 25°C | max 1176 mW | 11 |
| Safety temperature TS | ISO1640/1 D-8 PACKAGE | max 150 °C | 11 |
| Voltage input threshold low (SDA1 and SCL1) VILT1 | SIDE 1; over recommended operating conditions | min 480 · max 560 mV | 12 |
| Voltage input threshold high (SDA1 and SCL1) VIHT1 | SIDE 1; over recommended operating conditions | min 520 · max 620 mV | 12 |
| Voltage input hysteresis VHYST1 | SIDE 1; VIHT1 – VILT1; over recommended operating conditions | min 50 · typ 60 mV | 12 |
| Low-level output voltage (SDA1 and SCL1) VOL1 | SIDE 1; 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA; over recommended operating conditions | min 570 · typ 650 · max 710 mV | 12 |
| Low-level output voltage to highlevel input voltage threshold difference, SDA1 and SCL1 ΔVOIT1 | SIDE 1; 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA; over recommended operating conditions | min 50 mV | 12 |
| Low-level output voltage (SDA2 and SCL2) VOL2 | SIDE 2; 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 50 mA; over recommended operating conditions | max 0.4 V | 12 |
| Input leakage currents (SDA1, SCL1, SDA2, and SCL2) |II| | BOTH SIDES; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; over recommended operating conditions | typ 0.01 · max 10 uA | 12 |
| Input capacitance to local ground (SDA1, SCL1, SDA2, and SCL2) CI | BOTH SIDES; VI = 0.4 × sin(2e6*πt) + VDDx / 2; over recommended operating conditions | typ 10 pF | 12 |
| Common-mode transient immunity CMTI | BOTH SIDES; VCM = 1000 V, see Common-Mode Transient Immunity Test Circuit; over recommended operating conditions | min 50 · typ 100 kV/us | 12 |
| Supply current, Side 2 ICC2 | ISO1640; 2.25 V ≤ VCC2 ≤ 2.75 V; VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2; R1 and R2 = Open, C1 and C2 = Open | typ 4.9 · max 6.6 mA | 13 |
| Supply current, Side 2 ICC2 | ISO1640; 2.25 V ≤ VCC2 ≤ 2.75 V; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; R1 and R2 = Open, C1 and C2 = Open | typ 2.7 · max 3.5 mA | 13 |
| Supply current, Side 1 ICC1 | ISO1640; 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2; R1 and R2 = Open, C1 and C2 = Open | typ 5.2 · max 7.1 mA | 13 |
| Supply current, Side 1 ICC1 | ISO1640; 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; R1 and R2 = Open, C1 and C2 = Open | typ 3 · max 4 mA | 13 |
| Supply current, Side 2 ICC2 | ISO1640; 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2; R1 and R2 = Open, C1 and C2 = Open | typ 4.9 · max 6.7 mA | 13 |
| Supply current, Side 2 ICC2 | ISO1640; 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; R1 and R2 = Open, C1 and C2 = Open | typ 2.8 · max 3.5 mA | 13 |
| Supply current, Side 1 ICC1 | ISO1640; 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2; R1 and R2 = Open, C1 and C2 = Open | typ 5.3 · max 7.2 mA | 14 |
| Supply current, Side 1 ICC1 | ISO1640; 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; R1 and R2 = Open, C1 and C2 = Open | typ 3 · max 4.1 mA | 14 |
| Supply current, Side 2 ICC2 | ISO1640; 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2; R1 and R2 = Open, C1 and C2 = Open | typ 5 · max 6.8 mA | 14 |
| Supply current, Side 2 ICC2 | ISO1640; 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2; R1 and R2 = Open, C1 and C2 = Open | typ 2.8 · max 3.6 mA | 14 |
| Time to recover from UVLO tUVLO | VCC1 > VCC1(UVLO+) or VCC2 > VCC2(UVLO+), I2C bus Idle; see tUVLO Test Circuit and Timing Diagrams | min 36 · typ 95 · max 151 us | 14 |
| Output signal fall time (SDA2 and SCL2) tf2 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 72 Ω, C2 = 400 pF | min 16 · typ 26.5 · max 40 ns | 15 |
| Output signal fall time (SDA2 and SCL2) tf2 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; 0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 72Ω, C2 = 400 pF | min 38 · typ 53.3 · max 78 ns | 15 |
| Low-to-high propagation delay, side 1 to side 2 tpLH1-2 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 20 · max 30 ns | 15 |
| High-to-low propagation delay, side 1 to side 2 tpHL1-2 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 80 · max 130 ns | 15 |
| Low-to-high propagation delay, side 2 to side 1(1) tpLH2-1 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 40 · max 48 ns | 15 |
| High-to-low propagation delay, side 2 to side 1(1) tpHL2-1 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 70 · max 100 ns | 15 |
| Pulse width distortion |tpHL1-2 – tpLH1-2| PWD1-2 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 60 · max 104 ns | 15 |
| Pulse width distortion(1) |tpHL2-1 – tpLH2-1| PWD2-1 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V | typ 25 · max 55 ns | 15 |
| Round-trip propagation delay on side 1(1) tLOOP1 | 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V; 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 72 Ω, C2 = 400 pF | typ 62 · max 74 ns | 15 |
| Output signal fall time (SDA1 and SCL1) tf1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF | min 8 · typ 17 · max 29 ns | 15 |
| Output signal fall time (SDA1 and SCL1) tf1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; 0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 953 Ω, C1 = 40 pF | min 15 · typ 25 · max 48 ns | 15 |
| Output signal fall time (SDA2 and SCL2) tf2 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω, C2 = 400 pF | min 14 · typ 23 · max 47 ns | 15 |
| Output signal fall time (SDA2 and SCL2) tf2 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; 0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 95.3 Ω, C2 = 400 pF | min 30 · typ 50 · max 100 ns | 15 |
| Low-to-high propagation delay, side 1 to side 2 tpLH1-2 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 21 · max 29 ns | 15 |
| High-to-low propagation delay, side 1 to side 2 tpHL1-2 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 59 · max 88 ns | 15 |
| Low-to-high propagation delay, side 2 to side 1(1) tpLH2-1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 40 · max 47 ns | 15 |
| High-to-low propagation delay, side 2 to side 1(1) tpHL2-1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 70 · max 100 ns | 15 |
| Pulse width distortion |tpHL1-2 – tpLH1-2| PWD1-2 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 39 · max 61 ns | 15 |
| Pulse width distortion(1) |tpHL2-1 – tpLH2-1| PWD2-1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF | typ 25 · max 48 ns | 15 |
| Round-trip propagation delay on side 1(1) tLOOP1 | 3 V ≤ VCC1, VCC2 ≤ 3.6 V; 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF | typ 65 · max 78 ns | 15 |
| Output signal fall time (SDA1 and SCL1) tf1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 1430 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF | min 6 · typ 16 · max 22 ns | 16 |
| Output signal fall time (SDA1 and SCL1) tf1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; 0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 1430 Ω, C1 = 40 pF | min 13 · typ 32 · max 48 ns | 16 |
| Output signal fall time (SDA2 and SCL2) tf2 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 143 Ω, C2 = 400 pF | min 10 · typ 24 · max 30 ns | 16 |
| Output signal fall time (SDA2 and SCL2) tf2 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; 0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 143 Ω, C2 = 400 pF | min 28 · typ 48 · max 76 ns | 16 |
| Low-to-high propagation delay, side 1 to side 2 tpLH1-2 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VI = 535 mV, VO = 0.7 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 21 · max 28 ns | 16 |
| High-to-low propagation delay, side 1 to side 2 tpHL1-2 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VI = 550 mV, VO = 0.3 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 51 · max 70 ns | 16 |
| Low-to-high propagation delay, side 2 to side 1(1) tpLH2-1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 51 · max 57 ns | 16 |
| High-to-low propagation delay, side 2 to side 1(1) tpHL2-1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 60 · max 88 ns | 16 |
| Pulse width distortion |tpHL1-2 – tpLH1-2| PWD1-2 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 30 · max 45 ns | 16 |
| Pulse width distortion(1) |tpHL2-1 – tpLH2-1| PWD2-1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF | typ 10 · max 34 ns | 16 |
| Round-trip propagation delay on side 1(1) tLOOP1 | 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V; 0.4 V ≤ VI ≤ 0.3 × VCCI, R1 = 1430 Ω, C1 = 40 pF, R2 = 143 Ω, C2 = 400 pF | typ 84 · max 96 ns | 16 |
Pins, by the datasheet
8- 1 VCC1
- Supply voltage, side 1. · p. 5
- 2 SDA1
- Serial data input / output, side 1. · p. 5
- 3 SCL1
- Serial clock input / output, side 1. · p. 5
- 4 GND1
- Ground, side 1. · p. 5
- 5 GND2
- Ground, side 2. · p. 5
- 6 SCL2
- Serial clock input / output, side 2. · p. 5
- 7 SDA2
- Serial data input / output, side 2. · p. 5
- 8 VCC2
- Supply voltage, side 2. · p. 5
Ordering codes, by the datasheet
1- ISO1640BDR
- SOIC D, 8 pins · Package quantity 3000; operating temperature -40 to 125 °C · p. 38
Parameters
19- CMTI(kV/us)
- 100kV/us
- Clock Direction
- Bidirectional
- Current - Supply
- 10.3mA
- Current - Supply(Max)
- 14mA
- Data Rate
- 1.7Mbps
- Features
- Hotswap
- Isolation Voltage(Vrms)
- 3000
- Junction Temperature(Max)
- 150℃
- Maximum I2C Clock
- 1.7MHz
- Operating Temperature
- -40℃~+125℃
- Operating Voltage
- 2.25V~5.5V
- Output Current per Pin(Max)
- 20mA
- Peak Output Current(Sink)
- 50mA
- Rise Time
- 16ns
- Thermal Resistance(Junction to Ambient)
- 106.3℃/W
- Thermal Resistance(Junction to Board)
- 52.5℃/W
- Thermal Resistance(Junction to Case)
- 38.5℃/W
- Voltage - Supply
- 2.25V~5.5V
- Voltage - Supply(Absolute Max)
- 6V
Order codes
1- ISO1640BDRLCSC C5122339
Pinout
8| Pin | Name | Type |
|---|---|---|
| 1 | VCC1 | Unspecified |
| 2 | SDA1 | Unspecified |
| 3 | SCL1 | Unspecified |
| 4 | GND1 | Unspecified |
| 5 | GND2 | Unspecified |
| 6 | SCL2 | Unspecified |
| 7 | SDA2 | Unspecified |
| 8 | VCC2 | Unspecified |
Open-source boards using it
All 6- 4 layers195 × 45 mm
- 4 layers180 × 130 mm
Shield
Nicolboy/KICAD-C2000-powershield
Shield d'isolation, alimentation et interconnexion pour TMS320 C2000, conçu sous KiCad 10.
213 partsCERN-OHL-S-2.0 - 2 layers33 × 18.7 mm
EasyISO
Protocentral/protocentral_easyiso_hardware
ProtoCentral easyISO isolated Qwiic adapter — hardware design files (CERN-OHL-P v2)
25 partsCERN-OHL-P-2.0 - 2 layers90 × 66 mm
- 4 layers175 × 40 mm
Show this part on your page
<iframe src="https://pcbkit.io/embed/parts/ti/ISO1640BD" title="ISO1640BD in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe><img src="https://pcbkit.io/embed/parts/ti/ISO1640BD.jpg" alt="ISO1640BD" width="1200" height="900">[](https://pcbkit.io/parts/ti/ISO1640BD)Questions
Is there a KiCad symbol and footprint for the ISO1640BD?
Yes. The symbol is EasyEDA_Cloud:ISO1640BDR and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the ISO1640BD?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the ISO1640BD datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the ISO1640BD?
JLCPCB lists it as part C5122339, with 4,848 in stock; the sellers' links on this page open their listings.
What can replace the ISO1640BD?
Parts like it in the library: the ISO1540D by Texas Instruments, the ADUM1250ARZ-RL7 by Analog Devices, the CA-IS3020S by Chipanalog and the CA-IS3021S by Chipanalog. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the ISO1640BD?
6 boards in 5 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
Parts like it
8
ISO1540D
SOIC-8-40℃~+125℃ 2500 50kV/us Bidirectional Bidirectional automatic direction、Open-drain buffer output SOIC-8 I2C Isolators ROHSTexas InstrumentsI2C IsolatorsADUM1250ARZ-RL7
SOIC-8-150mil-40℃~+105℃ 1MHz 2500 30mA 35kV/us 3V~5.5V Bidirectional Bidirectional automatic direction、Open-drain buffer output、Hotswap SOIC-8-150mil I2C Isolators ROHSAnalog DevicesI2C IsolatorsCA-IS3020S
SOIC-8-55℃~+125℃ 150kV/us 5000 Bidirectional SOIC-8 I2C Isolators ROHSChipanalogI2C IsolatorsCA-IS3021S
SOIC-8-40℃~+125℃ 150kV/us 3750 Unidirectional SOIC-8 I2C Isolators ROHSChipanalogI2C IsolatorsADUM1250ARZ-RL7-HXY
SOP-8SOP-8 I2C Isolators ROHSHXY MOSFETI2C IsolatorsADUM1251ARZ-RL7
SOIC-8-40℃~+105℃ 2500 35kV/us Bidirectional SOIC-8 I2C Isolators ROHSAnalog DevicesI2C IsolatorsISO1541DR(TOKMAS)
SOIC-8-40℃~+125℃ 3000 88kV/us Bidirectional Bidirectional automatic direction、Open-drain buffer output SOIC-8 I2C Isolators ROHSTokmasI2C IsolatorsCA-IS3020WG
SOIC-8-WWBSOIC-8-WWB I2C Isolators ROHSChipanalogI2C Isolators