DRV8300DPW

Texas InstrumentsExtended

-40℃~+125℃ 1.5A 3 5V~20V 750mA、1.5A 800uA Three Phase TSSOP-20 Brushless DC (BLDC) Motor Driver ROHS

Part id: ti/DRV8300DPW
Category: Brushless DC (BLDC) Motor Driver
Package: TSSOP-20
Pins: 20
In stock: 7,388 at JLCPCB (C3036056)
Used on: 6 open-source boards

Overview

The DRV8300DPW is a brushless DC (BLDC) Motor Driver made by Texas Instruments in a TSSOP-20 package with 20 pins. -40℃~+125℃ 1.5A 3 5V~20V 750mA、1.5A 800uA Three Phase TSSOP-20 Brushless DC (BLDC) Motor Driver ROHS.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:DRV8300DPWRQ1, from EasyEDA) and its footprint (Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 7,388 are in stock at JLCPCB (part C3036056). 6 open-source boards in 5 repositories on GitHub use it.

Symbol

EasyEDA_Cloud:DRV8300DPWRQ1From EasyEDA

Footprint

Package_SO:TSSOP-20_4.4x6.5mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 5 V · GVDD, recommended operating min · p. 6
Supply, most: 20 V · GVDD, recommended operating max · p. 6
Supply, absolute maximum: 21.5 V · GVDD, absolute max · p. 6
Works from: -40 °C · operating ambient min · p. 6
Works up to: 125 °C · operating ambient max · p. 6
Junction, hottest: 150 °C · operating junction max · p. 7
Takes working: 825 µA · GVDD active mode typical, switching at 20 kHz, no FETs connected · p. 7
Takes asleep: 800 µA · GVDD standby mode typical, INHx = INLX = 0 · p. 7
Junction to air (PW (TSSOP)): 97.4 K/W · junction-to-ambient thermal resistance · p. 7
Junction to case (PW (TSSOP)): 38.3 K/W · junction-to-case top thermal resistance · p. 7
Junction to board (PW (TSSOP)): 48.8 K/W · junction-to-board thermal resistance · p. 7
Edge: 12 ns · GLx fall time typical, CLOAD = 1000 pF, VGVDD = VBSTx - VSHx > 8V, SHx = 0V · p. 8

What it is and has

Gate driver: 100-V three-phase half-bridge · p. 1
MOSFET type: N-channel · p. 1
Bootstrap diodes: Integrated · p. 1
Gate drive architecture: Bootstrap · p. 1
Peak source current: 750 mA · p. 1
Peak sink current: 1.5 A · p. 1
Battery support: Up to 15S · p. 1
Cross conduction prevention: Built in · p. 1
Fixed deadtime: 200 nS, TSSOP package variants · p. 1
Logic input compatibility: 3.3 V and 5 V · p. 1
Protection: BST undervoltage lockout · p. 1
Protection: GVDD undervoltage · p. 1
Package: TSSOP (20), 6.40 mm × 4.40 mm · p. 1

Around it

cap 10-uF: between GVDD and GND; At least 10-uF local capacitance; GVDD-rated X5R or X7R ceramic. · p. 5

Specifications

Parameter	Conditions	As printed	Page
Gate driver regulator pin voltage	GVDD	min -0.3 · max 21.5 V	6
Bootstrap pin voltage	BSTx	min -0.3 · max 125 V	6
Bootstrap pin voltage	BSTx with respect to SHx	min -0.3 · max 21.5 V	6
Logic pin voltage	INHx, INLx; maximum VGVDD+0.3 V	min -0.3 V	6
High-side gate drive pin voltage	GHx	min -22 · max 125 V	6
High-side gate drive pin voltage	GHx with respect to SHx	min -0.3 · max 22 V	6
Transient 500-ns high-side gate drive pin voltage	GHx with respect to SHx	min -5 · max 22 V	6
Low-side gate drive pin voltage	GLx; maximum VGVDD+0.3 V	min -0.3 V	6
Transient 500-ns low-side gate drive pin voltage	GLx; maximum VGVDD+0.3 V	min -5 V	6
High-side source pin voltage	SHx	min -22 · max 110 V	6
Ambient temperature, TA TA		min -40 · max 125 °C	6
Junction temperature, TJ TJ		min -40 · max 150 °C	6
Storage temperature, Tstg Tstg		min -65 · max 150 °C	6
Electrostatic discharge V(ESD)	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1); rating ±1000 V	max 1000 V	6
Electrostatic discharge V(ESD)	Charged device model (CDM), per JEDEC specification JESD22-C101(2); rating ±250 V	max 250 V	6
Power supply voltage VGVDD	GVDD	min 5 · max 20 V	6
High-side source pin voltage VSHx	SHx	min -2 · max 85 V	6
Transient 2us high-side source pin voltage VSHx	SHx	min -22 · max 85 V	6
Bootstrap pin voltage VBST	BSTx	min 5 · max 105 V	6
Bootstrap pin voltage VBST	BSTx with respect to SHx	min 5 · max 20 V	6
Logic input voltage VIN	INHx, INLx; maximum GVDD	min 0 V	6
PWM frequency fPWM	INHx, INLx	min 0 · max 200 kHz	6
Slew rate on SHx pin (DRV8300D and DRV8300DI) VSHSL	DRV8300D	max 2 V/ns	6
Capacitor between BSTx and SHx (DRV8300D and DRV8300DI) CBOOT	DRV8300D	max 1 uF	6
Operating ambient temperature TA		min -40 · max 125 °C	6
Operating junction temperature TJ		min -40 · max 150 °C	7
Junction-to-ambient thermal resistance RθJA	PW (TSSOP), 20 PINS	typ 97.4 °C/W	7
Junction-to-case (top) thermal resistance RθJC(top)	PW (TSSOP), 20 PINS	typ 38.3 °C/W	7
Junction-to-board thermal resistance RθJB	PW (TSSOP), 20 PINS	typ 48.8 °C/W	7
Junction-to-top characterization parameter ΨJT	PW (TSSOP), 20 PINS	typ 4.3 °C/W	7
Junction-to-board characterization parameter ΨJB	PW (TSSOP), 20 PINS	typ 48.4 °C/W	7
GVDD standby mode current IGVDD	INHx = INLX = 0; VBSTx = VGVDD	min 400 · typ 800 · max 1400 uA	7
GVDD active mode current IGVDD	INHx = INLX = Switching @20kHz; VBSTx = VGVDD; NO FETs connected	min 400 · typ 825 · max 1400 uA	7
Bootstrap pin leakage current ILBSx	VBSTx = VSHx = 85V; VGVDD = 0V	min 2 · typ 4 · max 7 uA	7
Bootstrap pin active mode transient leakage current ILBS_TRAN	INHx = Switching@20kHz	min 30 · typ 105 · max 220 uA	7
Bootstrap pin active mode leakage static current ILBS_DC	INHx = High	min 30 · typ 85 · max 150 uA	7
High-side source pin leakage current ILSHx	INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V	min 30 · typ 55 · max 80 uA	7
Input logic low voltage VIL	INLx, INHx pins	max 0.8 V	7
Input logic high voltage VIH	INLx, INHx pins	min 2 V	7
Input hysteresis VHYS	INLx, INHx pins	min 40 · typ 100 · max 260 mV	7
INLx Input logic low current IIL_INLx	VPIN (Pin Voltage) = 0 V; INLx in non-inverting mode	min -1 · typ 0 · max 1 uA	7
INLx Input logic high current IIH_INLx	VPIN (Pin Voltage) = 5 V; INLx in non-inverting mode	min 5 · typ 20 · max 30 uA	7
INHx, MODE Input logic low current IIL	INHx; VPIN (Pin Voltage) = 0 V;	min -1 · typ 0 · max 1 uA	7
INHx, MODE Input logic high current IIH	INHx; VPIN (Pin Voltage) = 5 V;	min 5 · typ 20 · max 30 uA	7
INHx Input pulldown resistance RPD_INHx	To GND	min 120 · typ 200 · max 280 kΩ	7
INLx Input pulldown resistance RPD_INLx	To GND, INLx in non-inverting mode	min 120 · typ 200 · max 280 kΩ	8
High-side gate drive low level voltage VGHx_LO	IGLx = -100 mA; VGVDD = 12V; No FETs connected	min 0 · typ 0.15 · max 0.35 V	8
High-side gate drive high level voltage (VBSTx - VGHx) VGHx_HI	IGHx = 100 mA; VGVDD = 12V; No FETs connected	min 0.3 · typ 0.6 · max 1.2 V	8
Low-side gate drive low level voltage VGLx_LO	IGLx = -100 mA; VGVDD = 12V; No FETs connected	min 0 · typ 0.15 · max 0.35 V	8
Low-side gate drive high level voltage (VGVDD - VGHx) VGLx_HI	IGHx = 100 mA; VGVDD = 12V; No FETs connected	min 0.3 · typ 0.6 · max 1.2 V	8
High-side peak source gate current IDRIVEP_HS	GHx-SHx = 12V	min 400 · typ 750 · max 1200 mA	8
High-side peak sink gate current IDRIVEN_HS	GHx-SHx = 0V	min 850 · typ 1500 · max 2100 mA	8
Low-side peak source gate current IDRIVEP_LS	GLx = 12V	min 400 · typ 750 · max 1200 mA	8
Low-side peak sink gate current IDRIVEN_LS	GLx = 0V	min 850 · typ 1500 · max 2100 mA	8
Input to output propagation delay tPD	INHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx	min 70 · typ 125 · max 180 ns	8
Matching propagation delay per phase tPD_match	GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx; typical ±4 ns	min -30 · typ 4 · max 30 ns	8
Matching propagation delay phase to phase tPD_match	GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx; typical ±4 ns	min -30 · typ 4 · max 30 ns	8
GLx rise time (10% to 90%) tR_GLx	CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V	min 10 · typ 24 · max 50 ns	8
GHx rise time (10% to 90%) tR_GHx	CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V	min 10 · typ 24 · max 50 ns	8
GLx fall time (90% to 10%) tF_GLx	CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V	min 5 · typ 12 · max 30 ns	8
GHx fall time (90% to 10%) tF_GHx	CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V	min 5 · typ 12 · max 30 ns	8
Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx tPW_MIN		min 40 · typ 70 · max 150 ns	8
Bootstrap diode forward voltage VBOOTD	DRV8300D; IBOOT = 100 uA	min 0.45 · typ 0.7 · max 0.85 V	8
Bootstrap diode forward voltage VBOOTD	DRV8300D; IBOOT = 100 mA	min 2 · typ 2.3 · max 3.1 V	8
Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) RBOOTD	DRV8300D; IBOOT = 100 mA and 80 mA	min 11 · typ 15 · max 25 Ω	8
Gate Driver Supply undervoltage lockout (GVDDUV) VGVDDUV	Supply rising	min 4.45 · typ 4.6 · max 4.7 V	8
Gate Driver Supply undervoltage lockout (GVDDUV) VGVDDUV	Supply falling	min 4.2 · typ 4.35 · max 4.4 V	8
Gate Driver Supply UV hysteresis VGVDDUV_HYS	Rising to falling threshold	min 250 · typ 280 · max 310 mV	8
Gate Driver Supply undervoltage deglitch time tGVDDUV		min 5 · typ 10 · max 13 us	9
Boot Strap undervoltage lockout (VBSTx - VSHx) VBSTUV	Supply rising	min 3.6 · typ 4.2 · max 4.8 V	9
Boot Strap undervoltage lockout (VBSTx - VSHx) VBSTUV	Supply falling	min 3.5 · typ 4 · max 4.5 V	9
Bootstrap UV hysteresis VBSTUV_HYS	Rising to falling threshold	typ 200 mV	9
Bootstrap undervoltage deglitch time tBSTUV		min 6 · typ 10 · max 22 us	9

Pins, by the datasheet

1 INHA: High-side gate driver control input; controls the high-side gate driver output. · p. 5
2 INHB: High-side gate driver control input; controls the high-side gate driver output. · p. 5
3 INHC: High-side gate driver control input; controls the high-side gate driver output. · p. 5
4 INLA: Low-side gate driver control input; controls the low-side gate driver output. · p. 5
5 INLB: Low-side gate driver control input; controls the low-side gate driver output. · p. 5
6 INLC: Low-side gate driver control input; controls the low-side gate driver output. · p. 5
7 GVDD: Gate driver supply input; connect at least 10-uF local GVDD-rated X5R or X7R ceramic capacitance to GND. · p. 5
8 GND: Device ground. · p. 5
9 GLC: Low-side gate driver output; connect to the low-side power MOSFET gate. · p. 5
10 GLB: Low-side gate driver output; connect to the low-side power MOSFET gate. · p. 5
11 GLA: Low-side gate driver output; connect to the low-side power MOSFET gate. · p. 5
12 SHC: High-side source sense input; connect to the high-side power MOSFET source. · p. 5
13 GHC: High-side gate driver output; connect to the high-side power MOSFET gate. · p. 5
14 BSTC: Bootstrap output; connect a capacitor between BSTC and SHC. · p. 5
15 SHB: High-side source sense input; connect to the high-side power MOSFET source. · p. 5
16 GHB: High-side gate driver output; connect to the high-side power MOSFET gate. · p. 5
17 BSTB: Bootstrap output; connect a capacitor between BSTB and SHB. · p. 5
18 SHA: High-side source sense input; connect to the high-side power MOSFET source. · p. 5
19 GHA: High-side gate driver output; connect to the high-side power MOSFET gate. · p. 5
20 BSTA: Bootstrap output; connect a capacitor between BSTA and SHA. · p. 5

Ordering codes, by the datasheet

DRV8300DPW: TSSOP (20) · DRV8300D with integrated bootstrap diodes; 6.40 mm × 4.40 mm body. · p. 1

Parameters

Current - Supply: 825uA
Drive Type: Three Phase
Features: Interleaved conduction protection
Integrated FETs: No
Interface: PWM
Junction Temperature(Max): 150℃
Number of Half Bridges: 3
Operating Temperature: -40℃~+125℃
Output Current: 1.5A
Peak Current: 1.5A
Quiescent Current(Iq): 800uA
Rise Time: 12ns
Standby Current: 800uA
Thermal Resistance(Junction to Ambient): 97.4℃/W
Thermal Resistance(Junction to Board): 48.8℃/W
Thermal Resistance(Junction to Case): 38.3℃/W
Voltage - Supply: 5V~20V
Voltage - Supply(Absolute Max): 21.5V

Order codes

DRV8300DPWRLCSC C3036056

Pinout

The pins of the DRV8300DPW
Pin	Name	Type
1	INHA	Unspecified
2	INHB	Unspecified
3	INHC	Unspecified
4	INLA	Unspecified
5	INLB	Unspecified
6	INLC	Unspecified
7	GVDD	Unspecified
8	GND	Unspecified
9	GLC	Unspecified
10	GLB	Unspecified
11	GLA	Unspecified
12	SHC	Unspecified
13	GHC	Unspecified
14	BSTC	Unspecified
15	SHB	Unspecified
16	GHB	Unspecified
17	BSTB	Unspecified
18	SHA	Unspecified
19	GHA	Unspecified
20	BSTA	Unspecified

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Parts like it

Questions

Is there a KiCad symbol and footprint for the DRV8300DPW?

Yes. The symbol is EasyEDA_Cloud:DRV8300DPWRQ1 and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the DRV8300DPW?

TSSOP-20, with 20 pins. Its footprint is drawn on this page.

Where is the DRV8300DPW datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the DRV8300DPW?

JLCPCB lists it as part C3036056, with 7,388 in stock; the sellers' links on this page open their listings.

What can replace the DRV8300DPW?

Parts like it in the library: the DRV8300NIPW by Texas Instruments, the TMP814PW by Texas Instruments, the LS7262C-TS by LSI/CSI and the DRV8300DPWRQ1 by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the DRV8300DPW?

6 boards in 5 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

DRV8300DPW

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Ordering codes, by the datasheet

Open-source boards using it

Fpv findland esc

Spin Coater

Inverter

BLDC Proto

SynchroDriverDS

Bldc

Parts like it

DRV8300NIPW

TMP814PW

LS7262C-TS

DRV8300DPWRQ1

BDR6315T

EG2134_N

LA6100