DAC8563SDGS
Texas Instruments
-40℃~+125℃ 14us 16 2 2.7V~5.5V 4LSB 900uA Integrated buffer、Power-on reset、Power-down mode、Programmable gain、Built-in reference source SPI Voltage Buffer VSSOP-10-0.5mm Digital to Analog Converters (DAC) ROHS
Extended
- Category
- Digital To Analog Converters (DAC)
- Package
- VSSOP-10-0.5mm
- Pins
- 10
Overview
The DAC8563SDGS is a digital To Analog Converter made by Texas Instruments in a VSSOP-10-0.5mm package with 10 pins. -40℃~+125℃ 14us 16 2 2.7V~5.5V 4LSB 900uA Integrated buffer、Power-on reset、Power-down mode、Programmable gain、Built-in reference source SPI Voltage Buffer VSSOP-10-0.5mm Digital to Analog Converters (DAC) ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:DAC7562TDGSR, from EasyEDA) and its footprint (EasyEDA_Cloud:VSSOP-10_L3.0-W3.0-P0.50-LS4.9-BL, from EasyEDA), ready for a KiCad board. 6,262 are in stock at JLCPCB (part C1554729).
Symbol
Footprint
From the datasheet
13- Supply, least
- 2.7 V · AVDD, recommended operating min · p. 5
- Supply, most
- 5.5 V · AVDD, recommended operating max · p. 5
- Supply, absolute maximum
- 6 V · AVDD to GND, absolute max · p. 5
- Works from
- -40 °C · Operating ambient temperature min · p. 5
- Works up to
- 125 °C · Operating ambient temperature max · p. 5
- Junction, hottest
- 150 °C · Junction temperature absolute max · p. 5
- Junction to air (DGS (VSSOP))
- 173.8 K/W · Junction-to-ambient thermal resistance · p. 5
- Junction to case (DGS (VSSOP))
- 48.5 K/W · Junction-to-case (top) thermal resistance · p. 5
- Junction to board (DGS (VSSOP))
- 79.9 K/W · Junction-to-board thermal resistance · p. 5
- Takes working
- 900 µA · AVDD, typical normal mode, 3.6–5.5 V, internal reference on, no load · p. 8
- Takes at most
- 1.6 mA · AVDD, max normal mode, 3.6–5.5 V, internal reference on, no load · p. 8
- Takes asleep
- 550 nA · AVDD, typical power-down, 3.6–5.5 V · p. 8
- Takes asleep
- 350 nA · AVDD, typical power-down, 2.7–3.6 V · p. 8
What it is and has
10- DAC resolution
- 16-bit · p. 1
- Relative accuracy
- 4 LSB INL · p. 1
- Internal reference
- 2.5 V, bidirectional reference pin · p. 1
- Reference initial accuracy
- ±5 mV maximum · p. 1
- Reference temperature drift
- 10 ppm/°C maximum · p. 1
- SPI
- 50 MHz, Schmitt-triggered inputs · p. 1
- Control functions
- LDAC and CLR · p. 1
- Output buffer
- Rail-to-rail operation · p. 1
- Package options
- WSON-10 (3 mm × 3 mm), VSSOP-10 · p. 1
- Resolution and relative accuracy
- 16-bit, 4 LSB INL · p. 1
Around it
3- cap 100 pF
- between AVDD and GND; Supply bypass; use with 1 nF and 0.1–1 uF capacitors. · p. 46
- cap 1 nF
- between AVDD and GND; Supply bypass; use with 100 pF and 0.1–1 uF capacitors. · p. 46
- cap 0.1–1 μF
- between AVDD and GND; Supply bypass capacitor. · p. 46
Specifications
79| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| AVDD to GND | Over operating ambient temperature range | min -0.3 · max 6 V | 5 |
| CLR, DIN, LDAC, SCLK and SYNC input voltage to GND | Maximum AVDD + 0.3 V | min -0.3 V | 5 |
| VOUT[A, B] to GND | Maximum AVDD + 0.3 V | min -0.3 V | 5 |
| VREFIN/VREFOUT to GND | Maximum AVDD + 0.3 V | min -0.3 V | 5 |
| Operating temperature range | min -40 · max 125 °C | 5 | |
| Junction temperature TJ | max 150 °C | 5 | |
| Storage temperature Tstg | min -65 · max 150 °C | 5 | |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; ±1000 V | max 1000 V | 5 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per JEDEC specification JESD22-C101; ±500 V | max 500 V | 5 |
| Supply voltage | AVDD to GND | min 2.7 · max 5.5 V | 5 |
| Digital input voltage | CLR, DIN, LDAC, SCLK and SYNC; maximum AVDD | min 0 V | 5 |
| Reference input voltage VREFIN | Maximum AVDD | min 0 V | 5 |
| Operating ambient temperature TA | min -40 · max 125 °C | 5 | |
| Junction-to-ambient thermal resistance RθJA | DGS (VSSOP), 10 pins | typ 173.8 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | DGS (VSSOP), 10 pins | typ 48.5 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | DGS (VSSOP), 10 pins | typ 79.9 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | DGS (VSSOP), 10 pins | typ 1.7 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | DGS (VSSOP), 10 pins | typ 68.4 °C/W | 5 |
| Resolution | DAC856x | min 16 Bits | 6 |
| Relative accuracy | DAC856x; Using line passing through codes 512 and 65,024; typical ±4, maximum ±12 | typ 4 · max 12 LSB | 6 |
| Differential nonlinearity | DAC856x; 16-bit monotonic; typical ±0.2, maximum ±1 | typ 0.2 · max 1 LSB | 6 |
| Offset error | Extrapolated from two-point line, unloaded; typical ±1, maximum ±4 | typ 1 · max 4 mV | 6 |
| Offset error drift | Typical ±2 | typ 2 uV/°C | 6 |
| Full-scale error | DAC register loaded with all 1s; typical ±0.03, maximum ±0.2 | typ 0.03 · max 0.2 % FSR | 6 |
| Zero-code error | DAC register loaded with all 0s | typ 1 · max 4 mV | 6 |
| Zero-code error drift | Typical ±2 | typ 2 uV/°C | 6 |
| Gain error | Extrapolated from two-point line, unloaded; typical ±0.01, maximum ±0.15 | typ 0.01 · max 0.15 % FSR | 6 |
| Gain temperature coefficient | Typical ±1 | typ 1 ppm FSR/°C | 6 |
| Output voltage range | Maximum AVDD | min 0 V | 6 |
| Output voltage settling time | DACs unloaded; transition between 1/4 scale and 3/4 scale, settling within ±0.024% FSR | typ 7 us | 6 |
| Output voltage settling time | RL = 1 MΩ; transition between 1/4 scale and 3/4 scale, settling within ±0.024% FSR | typ 10 us | 6 |
| Slew rate | Measured between 20%–80% of a full-scale transition | typ 0.75 V/us | 6 |
| Capacitive load stability | RL = ∞ | typ 1 nF | 6 |
| Capacitive load stability | RL = 2 kΩ | typ 3 nF | 6 |
| Code-change glitch impulse | 1-LSB change around major carry | typ 0.1 nV-s | 6 |
| Digital feedthrough | SCLK toggling, SYNC high | typ 0.1 nV-s | 6 |
| Power-on glitch impulse | RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V | typ 40 mV | 6 |
| Channel-to-channel dc crosstalk | Full-scale swing on adjacent channel, Internal reference | typ 15 uV | 6 |
| DC output impedance | At mid-scale input | typ 5 Ω | 6 |
| Short-circuit current | DAC outputs at full-scale, DAC outputs shorted to GND | typ 40 mA | 6 |
| Power-up time, including settling time | Coming out of power-down mode | typ 50 us | 6 |
| DAC output noise density | TA = 25°C, at mid-scale input, fOUT = 1 kHz | typ 90 nV/√Hz | 6 |
| DAC output noise | TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz | typ 2.6 uVPP | 6 |
| Input-pin leakage current | Typical ±0.1 | min -1 · typ 0.1 · max 1 uA | 7 |
| Logic input LOW voltage VIL | min 0 · max 0.8 V | 7 | |
| Pin capacitance | max 3 pF | 7 | |
| External reference current | External VREF = 2.5 V (when internal reference is disabled), all channels active using gain = 1 | typ 15 uA | 7 |
| Reference input impedance | Internal reference disabled, gain = 1 | typ 170 kΩ | 7 |
| Reference input impedance | Internal reference disabled, gain = 2 | typ 85 kΩ | 7 |
| Output voltage | REFERENCE OUTPUT; TA = 25°C | min 2.495 · typ 2.5 · max 2.505 V | 7 |
| Initial accuracy | REFERENCE OUTPUT; TA = 25°C; typical ±0.1 | min -5 · typ 0.1 · max 5 mV | 7 |
| Output-voltage temperature drift | REFERENCE OUTPUT | typ 4 · max 10 ppm/°C | 7 |
| Output-voltage noise | REFERENCE OUTPUT; f = 0.1 Hz to 10 Hz | typ 12 uVPP | 7 |
| Output-voltage noise density (high-frequency noise) | TA = 25°C, f = 1 kHz, CL = 0 uF | typ 250 nV/√Hz | 7 |
| Output-voltage noise density (high-frequency noise) | TA = 25°C, f = 1 MHz, CL = 0 uF | typ 30 nV/√Hz | 7 |
| Output-voltage noise density (high-frequency noise) | TA = 25°C, f = 1 MHz, CL = 4.7 uF | typ 10 nV/√Hz | 7 |
| Load regulation, sourcing | REFERENCE OUTPUT; TA = 25°C | typ 20 uV/mA | 7 |
| Load regulation, sinking | REFERENCE OUTPUT; TA = 25°C | typ 185 uV/mA | 7 |
| Output-current load capability | REFERENCE OUTPUT; ±20 mA | typ 20 mA | 7 |
| Line regulation | REFERENCE OUTPUT; TA = 25°C | typ 50 uV/V | 7 |
| Long-term stability or drift (aging) | REFERENCE OUTPUT; TA = 25°C, time = 0 to 1900 hours | typ 100 ppm | 7 |
| Thermal hysteresis | REFERENCE OUTPUT; First cycle | typ 200 ppm | 7 |
| Thermal hysteresis | REFERENCE OUTPUT; Additional cycles | typ 50 ppm | 7 |
| Power supply current IDD | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.25 · max 0.5 mA | 8 |
| Power supply current IDD | AVDD = 3.6 V to 5.5 V, normal mode, internal reference on; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.9 · max 1.6 mA | 8 |
| Power supply current IDD | AVDD = 3.6 V to 5.5 V, power-down modes; TA = –40°C to 105°C; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.55 · max 2 uA | 8 |
| Power supply current IDD | AVDD = 3.6 V to 5.5 V, power-down modes; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.55 · max 4 uA | 8 |
| Power supply current IDD | AVDD = 2.7 V to 3.6 V, normal mode, internal reference off; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.2 · max 0.4 mA | 8 |
| Power supply current IDD | AVDD = 2.7 V to 3.6 V, normal mode, internal reference on; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.73 · max 1.4 mA | 8 |
| Power supply current IDD | AVDD = 2.7 V to 3.6 V, power-down modes; TA = –40°C to 105°C; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.35 · max 2 uA | 8 |
| Power supply current IDD | AVDD = 2.7 V to 3.6 V, power-down modes; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.35 · max 3 uA | 8 |
| Power dissipation | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.9 · max 2.75 mW | 8 |
| Power dissipation | AVDD = 3.6 V to 5.5 V, normal mode, internal reference on; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 3.2 · max 8.8 mW | 8 |
| Power dissipation | AVDD = 3.6 V to 5.5 V, power-down modes; TA = –40°C to 105°C; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 2 · max 11 uW | 8 |
| Power dissipation | AVDD = 3.6 V to 5.5 V, power-down modes; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 2 · max 22 uW | 8 |
| Power dissipation | AVDD = 2.7 V to 3.6 V, normal mode, internal reference off; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.54 · max 1.44 mW | 8 |
| Power dissipation | AVDD = 2.7 V to 3.6 V, normal mode, internal reference on; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 1.97 · max 5 mW | 8 |
| Power dissipation | AVDD = 2.7 V to 3.6 V, power-down modes; TA = –40°C to 105°C; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.95 · max 7.2 uW | 8 |
| Power dissipation | AVDD = 2.7 V to 3.6 V, power-down modes; input code = mid-scale, no load, VINH = AVDD, VINL = GND | typ 0.95 · max 10.8 uW | 8 |
Pins, by the datasheet
10- 1 VOUTA
- Analog output voltage from DAC-A. · p. 4
- 2 VOUTB
- Analog output voltage from DAC-B. · p. 4
- 3 GND
- Ground reference point for all circuitry on the device. · p. 4
- 4 LDAC
- Connect permanently to GND or hold low before commands for synchronous updates; a falling edge simultaneously updates DAC output registers in asynchronous mode. · p. 4
- 5 CLR
- Falling-edge-sensitive asynchronous clear loads mid-scale into all input and DAC registers; activation during a write aborts the write. · p. 4
- 6 SYNC
- Active-low frame synchronization with Schmitt-trigger input; enables the shift register, with data sampled on falling clock edges and DAC update after the 24th falling edge. · p. 4
- 7 SCLK
- Schmitt-trigger serial clock input supporting transfer rates up to 50 MHz. · p. 4
- 8 DIN
- Schmitt-trigger serial data input clocked into the 24-bit shift register on each falling serial clock edge. · p. 4
- 9 AVDD
- Power-supply input, 2.7 V to 5.5 V. · p. 4
- 10 VREFIN/VREFOUT
- Bidirectional voltage reference pin; provides a 2.5-V output when the internal reference is used. · p. 4
Parameters
18- Current - Supply
- 900uA
- Current - Supply(Max)
- 1.6mA
- Function
- Programmable gain
- Integral non - linearity
- 4LSB
- Interface
- SPI
- Junction Temperature(Max)
- 150℃
- Number of Channels
- 2
- Operating Temperature
- -40℃~+125℃
- Output Type
- Voltage Buffer
- Quiescent Current (Iq)
- 900uA
- Resolution (Bits)
- 16
- Settling Time
- 14us
- Standby Current
- 550nA
- Thermal Resistance(Junction to Ambient)
- 173.8℃/W
- Thermal Resistance(Junction to Board)
- 79.9℃/W
- Thermal Resistance(Junction to Case)
- 48.5℃/W
- Voltage - Supply
- 2.7V~5.5V
- Voltage - Supply(Absolute Max)
- 6V
Order codes
3- DAC8563SDGSRLCSC C1554729
- DAC8563SDGSRLCSC C22400019
- DAC8563SDGSTLCSC C2679492
Pinout
10| Pin | Name | Type |
|---|---|---|
| 1 | VOUTA | Unspecified |
| 2 | VOUTB | Unspecified |
| 3 | GND | Unspecified |
| 4 | LDAC# | Unspecified |
| 5 | CLR# | Unspecified |
| 6 | SYNC# | Unspecified |
| 7 | SCLK | Unspecified |
| 8 | DIN | Unspecified |
| 9 | AVDD | Unspecified |
| 10 | VREFIN/VREFOUT | Unspecified |
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Is there a KiCad symbol and footprint for the DAC8563SDGS?
Yes. The symbol is EasyEDA_Cloud:DAC7562TDGSR and the footprint EasyEDA_Cloud:VSSOP-10_L3.0-W3.0-P0.50-LS4.9-BL, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the DAC8563SDGS?
VSSOP-10-0.5mm, with 10 pins. Its footprint is drawn on this page.
Where is the DAC8563SDGS datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the DAC8563SDGS?
JLCPCB lists it as part C1554729, with 6,262 in stock; the sellers' links on this page open their listings.
What can replace the DAC8563SDGS?
Parts like it in the library: the DAC80501MDGS by Texas Instruments, the DAC124S085CIMM by Texas Instruments, the DAC082S085CIMMX by Texas Instruments and the DAC104S085CIMM by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Parts like it
8
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