DAC80501MDGS
Texas InstrumentsExtended
-40℃~+125℃ 1 15uA 16 1LSB 2.7V~5.5V 3us I2C、SPI Voltage Buffer VSSOP-10-0.5mm Digital to Analog Converters (DAC) ROHS
- Part id
- ti/DAC80501MDGS
- Category
- Digital To Analog Converters (DAC)
- Package
- VSSOP-10-0.5mm
- Pins
- 10
- In stock
- 2,163 at JLCPCB (C1852032)
Overview
The DAC80501MDGS is a digital To Analog Converter made by Texas Instruments in a VSSOP-10-0.5mm package with 10 pins. -40℃~+125℃ 1 15uA 16 1LSB 2.7V~5.5V 3us I2C、SPI Voltage Buffer VSSOP-10-0.5mm Digital to Analog Converters (DAC) ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:DAC80501MDGSR, from EasyEDA) and its footprint (EasyEDA_Cloud:VSSOP-10_L3.0-W3.0-P0.50-LS4.9-BL, from EasyEDA), ready for a KiCad board. 2,163 are in stock at JLCPCB (part C1852032).
Symbol
Footprint
From the datasheet
13- Supply, least
- 2.7 V · VDD, recommended operating min · p. 4
- Supply, most
- 5.5 V · VDD, recommended operating max · p. 4
- Supply, absolute maximum
- 6 V · VDD to AGND, absolute max · p. 4
- Works from
- -40 °C · Operating free-air temperature min · p. 4
- Works up to
- 125 °C · Operating free-air temperature max · p. 4
- Junction, hottest
- 150 °C · Junction temperature absolute max · p. 4
- A pin gives at most
- 10 mA · Current into any digital pin, absolute max · p. 4
- Takes working
- 1.5 mA · VDD typical, normal mode, internal reference enabled, full scale, SPI static · p. 8
- Takes at most
- 2 mA · VDD max, normal mode, internal reference enabled, full scale, SPI static · p. 8
- Takes asleep
- 15 µA · VDD typical, DAC and internal reference powered down · p. 8
- Junction to air (DGS (VSSOP))
- 170.1 K/W · Junction-to-ambient thermal resistance · p. 5
- Junction to case (DGS (VSSOP))
- 60.5 K/W · Junction-to-case top thermal resistance · p. 5
- Junction to board (DGS (VSSOP))
- 92.6 K/W · Junction-to-board thermal resistance · p. 5
What it is and has
8- Resolution
- 16-bit · p. 3
- Reference
- Internal (default) or external · p. 3
- Power-on reset
- Midscale · p. 3
- Linearity
- 1-LSB INL and DNL maximum · p. 1
- Buffered output range
- 5 V, 2.5 V, or 1.25 V · p. 1
- SPI
- 3-wire, up to 50 MHz · p. 1
- I2C
- 2-wire · p. 1
- Package options
- 8-pin WSON and 10-pin VSSOP · p. 1
Specifications
90| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Input voltage | VDD to AGND | min -0.3 · max 6 V | 4 |
| Input voltage | VREFIO to AGND; maximum VDD + 0.3 V | min -0.3 V | 4 |
| Input voltage | Digital inputs to AGND; maximum VDD + 0.3 V | min -0.3 V | 4 |
| Output voltage | VOUT to AGND; maximum VDD + 0.3 V | min -0.3 V | 4 |
| Input current | Current into any digital pins | min -10 · max 10 mA | 4 |
| Input current | Current into VDD, AGND, VOUT | min -30 · max 30 mA | 4 |
| Input current | Current into VREFIO | min -100 · max 100 mA | 4 |
| Junction temperature TJ | min -40 · max 150 °C | 4 | |
| Storage temperature Tstg | min -65 · max 150 °C | 4 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; rated value ±2000 V | max 2000 V | 4 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; rated value ±1000 V | max 1000 V | 4 |
| Positive supply voltage to ground VDD to AGND | min 2.7 · max 5.5 V | 4 | |
| Input high voltage VIH | min 1.62 V | 4 | |
| Input low voltage VIL | max 0.45 V | 4 | |
| VREFIO to AGND VREFIO to AGND | 2.7 V ≤ VDD < 3.3 V, reference divider disabled (REF-DIV bit = 0); maximum 0.5 × (VDD – 0.2) | min 1.2 V | 4 |
| VREFIO to AGND VREFIO to AGND | 2.7 V ≤ VDD < 3.3 V, reference divider enabled (REF-DIV bit = 1); maximum (VDD – 0.2) | min 2.4 V | 4 |
| VREFIO to AGND VREFIO to AGND | 3.3 V ≤ VDD ≤ 5.5 V, reference divider disabled (REF-DIV bit = 0); maximum 0.5 × VDD | min 1.2 V | 4 |
| VREFIO to AGND VREFIO to AGND | 3.3 V ≤ VDD ≤ 5.5 V, reference divider enabled (REF-DIV bit = 1); maximum VDD | min 2.4 V | 4 |
| Operating temperature TA | Operating free-air temperature | min -40 · max 125 °C | 4 |
| Junction-to-ambient thermal resistance RθJA | DGS (VSSOP), 10 PINS | typ 170.1 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | DGS (VSSOP), 10 PINS | typ 60.5 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | DGS (VSSOP), 10 PINS | typ 92.6 °C/W | 5 |
| Junction-to-top characterization parameter ΨJT | DGS (VSSOP), 10 PINS | typ 7.8 °C/W | 5 |
| Junction-to-board characterization parameter ΨJB | DGS (VSSOP), 10 PINS | typ 90.7 °C/W | 5 |
| Resolution | DAC80501 | min 16 Bits | 5 |
| Integral nonlinearity(1) INL | min -1 · max 1 LSB | 5 | |
| Differential nonlinearity(1) DNL | min -1 · max 1 LSB | 5 | |
| Total unadjusted error(1) TUE | DAC80501, reference divider disabled (REF-DIV bit = 0) | min -0.08 · typ -0.02 · max 0.08 %FSR | 5 |
| Total unadjusted error(1) TUE | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | min -0.07 · typ 0.025 · max 0.07 %FSR | 5 |
| Zero code error(1) | DAC loaded with zero scale code | min -1.5 · typ 0.5 · max 1.5 mV | 5 |
| Zero code error temperature coefficient(1) | Typical value ±2 uV/°C | typ 2 uV/°C | 5 |
| Offset error(1) | min -1.5 · typ 0.5 · max 1.5 mV | 5 | |
| Offset error temperature coefficient (1) | Typical value ±2 uV/°C | typ 2 uV/°C | 5 |
| Gain error(1) | DAC80501, reference divider disabled (REF-DIV bit = 0) | min -0.08 · typ -0.02 · max 0.08 %FSR | 5 |
| Gain error(1) | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | min -0.07 · typ 0.025 · max 0.07 %FSR | 5 |
| Gain error temperature coefficient(1) | Typical value ±1 ppm FSR/°C | typ 1 ppm FSR/°C | 5 |
| Full-scale error(1) | DAC80501, DAC loaded with full scale, reference divider disabled (REF-DIV bit = 0) | min -0.08 · typ -0.02 · max 0.08 %FSR | 6 |
| Full-scale error(1) | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | min -0.07 · typ 0.025 · max 0.07 %FSR | 6 |
| Full-scale error temperature coefficient(1) | Typical value ±2 ppm FSR/°C | typ 2 ppm FSR/°C | 6 |
| Output voltage VO | BUFF-GAIN bit set to 1, REF-DIV bit set to 0; maximum 2 × VREFIO | min 0 V | 6 |
| Output voltage VO | BUFF-GAIN bit set to 1, REF-DIV bit set to 1; maximum VREFIO | min 0 V | 6 |
| Output voltage VO | BUFF-GAIN bit set to 0, REF-DIV bit set to 1; maximum 0.5 × VREFIO | min 0 V | 6 |
| Resistive load(2) RLOAD | VDD = 2.7 V | min 0.25 kΩ | 6 |
| Resistive load(2) RLOAD | VDD = 5.5 V | min 0.5 kΩ | 6 |
| Capacitive load(2) CLOAD | RLOAD = infinite | max 2 nF | 6 |
| Capacitive load(2) CLOAD | RLOAD = 2 kΩ | max 10 nF | 6 |
| Load regulation | DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA | typ 80 uV/mA | 6 |
| Short circuit current | Full scale output shorted to AGND | typ 30 mA | 6 |
| Short circuit current | Zero output shorted to VDD | typ 30 mA | 6 |
| Output voltage headroom | to VDD, DAC at full code, IOUT = 10 mA (sourcing) | min 0.3 · typ 0.1 V | 6 |
| Output voltage footroom | to AGND, DAC at zero code, IOUT = 10 mA (sinking) | min 0.3 V | 6 |
| DC small signal output impedance ZO | DAC at midscale | typ 0.1 Ω | 6 |
| DC small signal output impedance ZO | DAC at code 256 | typ 10 Ω | 6 |
| DC small signal output impedance ZO | DAC at code 65279 | typ 10 Ω | 6 |
| Power supply rejection ratio (DC) | DAC at midscale; VDD = 5 V ± 10% | typ 0.15 mV/V | 6 |
| Output voltage drift vs time | TA = 35°C, VOUT = midscale, 1900 hr | typ 20 ppm of FSR | 6 |
| Reference input impedance (VREFIO) ZVREFIO | typ 100 kΩ | 6 | |
| Reference input capacitance (VREFIO) CVREFIO | typ 5 pF | 6 | |
| Output (initial accuracy)(3) | Voltage reference output; TA = 25°C; characterized on 8-pin DQF package | min 2.4975 · max 2.5025 V | 7 |
| Output drift(3) | Voltage reference output; DAC80501; characterized on 8-pin DQF package | max 5 ppm/℃ | 7 |
| Output impedance(3) | Voltage reference output; characterized on 8-pin DQF package | typ 0.1 Ω | 7 |
| Output noise(3) | Voltage reference output; 0.1 Hz to 10 Hz; characterized on 8-pin DQF package | typ 14 uVPP | 7 |
| Output noise density(3) | Voltage reference output; measured at 10 kHz, reference load = 10 nF; characterized on 8-pin DQF package | typ 140 nV/√ Hz | 7 |
| Load current(3) | Voltage reference output; –0.5 mV < ΔVref < 0.5 mV; typical value ±5 mA; characterized on 8-pin DQF package | typ 5 mA | 7 |
| Load regulation(3) | Voltage reference output; sourcing and sinking; characterized on 8-pin DQF package | typ 90 uV/mA | 7 |
| Line regulation(3) | Voltage reference output; characterized on 8-pin DQF package | typ 20 uV/V | 7 |
| Output voltage drift vs time(3) | Voltage reference output; TA = 25°C, 1600 hr; characterized on 8-pin DQF package | typ 50 ppm of FSR | 7 |
| Thermal hysteresis(3) | Voltage reference output; 1st cycle; characterized on 8-pin DQF package | typ 500 uV | 7 |
| Thermal hysteresis(3) | Voltage reference output; additional cycle; characterized on 8-pin DQF package | typ 25 uV | 7 |
| Slew rate(4) | VDD = 5.5 V, VREFIO = 2.5 V; BUFF-GAIN bit = 1 | typ 2 V/us | 7 |
| Power on glitch magnitude | CLOAD = 50 pF | typ 200 mV | 7 |
| Output noise(4) Vn | 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V; BUFF-GAIN bit = 1 | typ 14 uVPP | 7 |
| Output noise(4) Vn | 100-kHz Bandwidth, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V; BUFF-GAIN bit = 1 | typ 23 uVrms | 7 |
| Output noise density Vn | Measured at 1 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2 × (BUFF-GAIN bit = 1) | typ 78 nV/√ Hz | 7 |
| Output noise density Vn | Measured at 10 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2 × (BUFF-GAIN bit = 1) | typ 74 nV/√ Hz | 7 |
| Output noise density Vn | Measured at 1 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1 × (BUFF-GAIN bit = 0) | typ 55 nV/√ Hz | 7 |
| Output noise density Vn | Measured at 10 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1 × (BUFF-GAIN bit = 0) | typ 50 nV/√ Hz | 7 |
| Spurious free dynamic range SFDR | 1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output | typ 70 dB | 7 |
| Total harmonic distortion THD | 1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output | typ 70 dB | 7 |
| Power supply rejection ratio (ac) | 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. (ac analysis) | typ 85 dB | 7 |
| Code change glitch impulse | Midcode ±1 LSB (including feedthrough) | typ 4 nV-s | 7 |
| Code change glitch magnitude | Midcode ±1 LSB (including feedthrough), gain = 1 × (BUFF-GAIN bit = 0) | typ 7.5 mV | 7 |
| Digital feedthrough | At SCLK = 1 MHz, DAC output at midscale | typ 4 nV-s | 8 |
| Hysteresis voltage | Digital inputs | typ 0.4 V | 8 |
| Input current | Digital inputs | min -5 · max 5 uA | 8 |
| Pin capacitance | Per pin | typ 10 pF | 8 |
| Current flowing into VDD IVDD | Normal mode, internal reference enabled, DAC at full scale, SPI static | typ 1.5 · max 2 mA | 8 |
| Current flowing into VDD IVDD | Normal mode, external reference = 2.5 V, DAC at full scale, SPI static | typ 1 · max 1.4 mA | 8 |
| Current flowing into VDD IVDD | DAC and Internal reference power-down | typ 15 uA | 8 |
| Current flowing into VREFIO IVREFIO | 0-V to 5-V range, midscale code | typ 25 uA | 8 |
Pins, by the datasheet
10- 1 VDD
- Analog supply voltage, 2.7 V to 5.5 V. · p. 3
- 2 VOUT
- Analog output voltage from the DAC. · p. 3
- 3 NC
- No connection. Leave floating. · p. 3
- 4 AGND
- Ground reference point for all circuitry on the device. · p. 3
- 5 SPI2C
- Interface select: 0 selects SPI and 1 selects I2C; keep static after power-up. · p. 3
- 6 SCLK/SCL
- Serial interface clock for SPI or I2C mode. · p. 3
- 7 SYNC/A0
- SPI active-low serial data enable and frame synchronization; I2C four-state address input 0. · p. 3
- 8 SDIN/SDA
- SPI serial data input clocked on falling SCLK edges; I2C bidirectional data line requiring an external pullup resistor to the supply. · p. 3
- 9 NC
- No connection. Leave floating. · p. 3
- 10 VREFIO
- Reference voltage output when using the internal reference, which is the default; reference input when using an external reference. · p. 3
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Questions
Is there a KiCad symbol and footprint for the DAC80501MDGS?
Yes. The symbol is EasyEDA_Cloud:DAC80501MDGSR and the footprint EasyEDA_Cloud:VSSOP-10_L3.0-W3.0-P0.50-LS4.9-BL, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the DAC80501MDGS?
VSSOP-10-0.5mm, with 10 pins. Its footprint is drawn on this page.
Where is the DAC80501MDGS datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the DAC80501MDGS?
JLCPCB lists it as part C1852032, with 2,163 in stock; the sellers' links on this page open their listings.
What can replace the DAC80501MDGS?
Parts like it in the library: the DAC8563SDGS by Texas Instruments, the DAC124S085CIMM by Texas Instruments, the DAC082S085CIMMX by Texas Instruments and the DAC104S085CIMM by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.