ADS131M04IPW

Q: Is there a KiCad symbol and footprint for the ADS131M04IPW?

Yes. The symbol is Analog_ADC:ADS131M04xPW and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the ADS131M04IPW?

TSSOP-20, with 20 pins. Its footprint is drawn on this page.

Q: Where is the ADS131M04IPW datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the ADS131M04IPW?

JLCPCB lists it as part C2862562, with 999 in stock; the sellers' links on this page open their listings.

Q: What can replace the ADS131M04IPW?

Parts like it in the library: the ADS131M02IPW by Texas Instruments, the ADS131M03IPW by Texas Instruments, the ADS131M08IPBSR by Texas Instruments and the ADS131M02IRUK by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the ADS131M04IPW?

8 boards in 5 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

Texas InstrumentsExtended

-40℃~+125℃ 2.7V~3.6V 24 4 4mA 64kHz 79dB 8.192MHz Built-in External Input buffer、Power-on reset、Integrated modulator、Synchronous triggering、Simultaneous sampling、Built-in digital filter SPI Sigma-Delta Support Yes TSSOP-20 Analog to Digital Converters (ADC) ROHS

Datasheet JLCPCB LCSC

Part id: ti/ADS131M04IPW
Category: Analog To Digital Converters (ADC)
Package: TSSOP-20
Pins: 20
In stock: 999 at JLCPCB (C2862562)
Used on: 8 open-source boards

Overview

The ADS131M04IPW is an analog To Digital Converter made by Texas Instruments in a TSSOP-20 package with 20 pins. -40℃~+125℃ 2.7V~3.6V 24 4 4mA 64kHz 79dB 8.192MHz Built-in External Input buffer、Power-on reset、Integrated modulator、Synchronous triggering、Simultaneous sampling、Built-in digital filter SPI Sigma-Delta Support Yes TSSOP-20 Analog to Digital Converters (ADC) ROHS.

PCBKit's library has its KiCad symbol (Analog_ADC:ADS131M04xPW, from KiCad's library) and its footprint (Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 999 are in stock at JLCPCB (part C2862562). 8 open-source boards in 5 repositories on GitHub use it.

Symbol

Analog_ADC:ADS131M04xPWFrom KiCad's library

Footprint

Package_SO:TSSOP-20_4.4x6.5mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 2.7 V · AVDD, normal operating modes, min · p. 6
Supply, most: 3.6 V · AVDD, normal operating modes, max · p. 6
Supply, least: 2.4 V · AVDD, standby and current-detect modes, min · p. 6
Supply, least: 1.65 V · DVDD, digital LDO bypassed, min · p. 6
Supply, most: 2 V · DVDD, digital LDO bypassed, max · p. 6
Supply, absolute maximum: 3.9 V · AVDD to AGND, absolute max · p. 5
Supply, absolute maximum: 2.2 V · DVDD to DGND, CAP tied to DVDD, absolute max · p. 5
Works from: -40 °C · Operating ambient temperature, min · p. 6
Works up to: 125 °C · Operating ambient temperature, max · p. 6
Junction, hottest: 150 °C · Junction temperature, absolute max · p. 5
Takes working: 3.9 mA · sum of AVDD and DVDD, high-resolution mode, SPI idle, typical · p. 8
Takes at most: 4.5 mA · sum of AVDD and DVDD, high-resolution mode, SPI idle, max · p. 8
Takes asleep: 1.3 µA · sum of AVDD and DVDD, standby mode, typical · p. 8
Junction to air (PW (TSSOP)): 94.9 K/W · Junction-to-ambient thermal resistance · p. 6
Junction to case (PW (TSSOP)): 34.9 K/W · Junction-to-case (top) thermal resistance · p. 6
Junction to board (PW (TSSOP)): 46.4 K/W · Junction-to-board thermal resistance · p. 6

What it is and has

ADC: 4-channel, simultaneously sampling, 24-bit, delta-sigma · p. 1
Differential inputs: 4, simultaneously sampling · p. 1
Data rate: Programmable up to 64 kSPS · p. 1
Programmable gain: Up to 128 · p. 1
Dynamic range: 102 dB at gain = 1, 4 kSPS · p. 1
Dynamic range: 80 dB at gain = 64, 4 kSPS · p. 1
Total harmonic distortion: –100 dB · p. 1
Channel phase calibration resolution: 244 ns at 8.192-MHz fCLKIN · p. 1
Crosstalk between channels: –120 dB · p. 1
Internal reference: Low-drift, 1.2 V · p. 1
CRC: Communications and register map · p. 1
Package options: 20-pin TSSOP or 20-pin WQFN · p. 1
Differential inputs: 4 simultaneously sampling · p. 1
Internal reference: Nominal 1.2 V · p. 19
Communication CRC: 16-bit input and output CRC · p. 28

Around it

cap 1 µF: between AVDD and AGND; Analog supply capacitor. · p. 4
cap 220 nF: between CAP and DGND; Digital LDO regulator output capacitor. · p. 4
cap 1 µF: between DVDD and DGND; Digital I/O supply capacitor. · p. 4

Specifications

120

Parameter	Conditions	As printed	Page
Power-supply voltage	AVDD to AGND	min -0.3 · max 3.9 V	5
Power-supply voltage	AGND to DGND	min -0.3 · max 0.3 V	5
Power-supply voltage	DVDD to DGND	min -0.3 · max 3.9 V	5
Power-supply voltage	DVDD to DGND, CAP tied to DVDD	min -0.3 · max 2.2 V	5
Power-supply voltage	CAP to DGND	min -0.3 · max 2.2 V	5
Input current	Continuous, all pins except power-supply pins	min -10 · max 10 mA	5
Temperature TJ	Junction	max 150 °C	5
Temperature Tstg	Storage	min -60 · max 150 °C	5
Electrostatic discharge V(ESD)	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1); rating ±2000 V	max 2000 V	5
Electrostatic discharge V(ESD)	Charged device model (CDM), per JEDEC specification JESD22-C101(2); rating ±500 V	max 500 V	5
Analog power supply	AVDD to AGND, normal operating modes; typ field is NOM	min 2.7 · typ 3 · max 3.6 V	6
Analog power supply	AVDD to AGND, standby and current-detect modes; typ field is NOM	min 2.4 · typ 3 · max 3.6 V	6
Analog power supply	AGND to DGND; typ field is NOM	min -0.3 · typ 0 · max 0.3 V	6
Digital power supply	DVDD to DGND; typ field is NOM	min 2.7 · typ 3 · max 3.6 V	6
Digital power supply	DVDD to DGND, DVDD shorted to CAP (digital LDO bypassed); typ field is NOM	min 1.65 · typ 1.8 · max 2 V	6
External clock frequency fCLKIN	High-resolution mode; typ field is NOM	min 0.3 · typ 8.192 · max 8.4 MHz	6
External clock frequency fCLKIN	Low-power mode; typ field is NOM	min 0.3 · typ 4.096 · max 4.15 MHz	6
External clock frequency fCLKIN	Very-low-power mode; typ field is NOM	min 0.3 · typ 2.048 · max 2.08 MHz	6
Duty cycle	External clock source; typ field is NOM	min 40 · typ 50 · max 60 %	6
Operating ambient temperature TA		min -40 · max 125 °C	6
Junction-to-ambient thermal resistance RθJA	PW (TSSOP), 20 pins	typ 94.9 °C/W	6
Junction-to-case (top) thermal resistance RθJC(top)	PW (TSSOP), 20 pins	typ 34.9 °C/W	6
Junction-to-board thermal resistance RθJB	PW (TSSOP), 20 pins	typ 46.4 °C/W	6
Junction-to-top characterization parameter ΨJT	PW (TSSOP), 20 pins	typ 2.7 °C/W	6
Junction-to-board characterization parameter ΨJB	PW (TSSOP), 20 pins	typ 46 °C/W	6
Input bias current IB	Gain = 1, 2, or 4, VINP = VINN = 0 V, IB = (IBP + IBN) / 2	typ 0.6 uA	7
Input bias current IB	Gain = 8, 16, 32, 64 or 128, VINP = VINN = 0 V, IB = (IBP + IBN) / 2	typ 0.2 uA	7
Differential input impedance Zin	Gain = 1, 2, or 4	typ 300 kΩ	7
Differential input impedance Zin	Gain = 8, 16, 32, 64, or 128; ±1 uA/V, current can flow either into or out of the input pin	typ 1 uA/V	7
Resolution		min 24 Bits	7
Data rate fDATA	High-resolution mode, fCLKIN = 8.192 MHz	min 250 SPS	7
Data rate fDATA	Low-power mode, fCLKIN = 4.096 MHz	min 125 SPS	7
Data rate fDATA	Very-low-power mode, fCLKIN = 2.048 MHz	min 62.5 SPS	7
Startup time	Measured from supplies at 90% to first DRDY falling edge	typ 0.5 ms	7
Integral nonlinearity (best fit) INL		typ 6 ppm of FSR	7
Offset error (input referred)	Global-chop mode disabled; typical ±175 uV	typ 175 uV	7
Offset error (input referred)	Global-chop mode, channel 0; typical ±35 uV	typ 35 uV	7
Offset error (input referred)	Global-chop mode, channels 1-3; typical ±15 uV	typ 15 uV	7
Offset drift	Global-chop mode disabled	typ 300 nV/°C	7
Offset drift	Global-chop mode	typ 200 nV/°C	7
Offset error time drift	1000 hours at 85°C, TSSOP package	typ 4 uV	7
Gain error	Typical ±0.1%	typ 0.1 %	7
Gain drift	Including internal reference	typ 8.5 ppm/°C	7
Gain error time drift	1000 hours at 85°C, TSSOP package	typ 400 ppm	7
Common-mode rejection ratio CMRR	At dc	typ 100 dB	7
Common-mode rejection ratio CMRR	fCM = 50 Hz or 60 Hz	typ 94 dB	7
Power-supply rejection ratio PSRR	AVDD at dc	typ 75 dB	7
Power-supply rejection ratio PSRR	DVDD at dc	typ 88 dB	7
Power-supply rejection ratio PSRR	AVDD supply, fPS = 50 Hz or 60 Hz	typ 78 dB	7
Power-supply rejection ratio PSRR	DVDD supply, fPS = 50 Hz or 60 Hz	typ 85 dB	7
Input-referred noise		typ 5.35 uVRMS	7
Input-referred noise	During fast-startup	typ 1.5 mVRMS	7
Dynamic range	Gain = 1	min 99 · typ 102 dB	7
Dynamic range	Gain = 64	typ 80 dB	7
Crosstalk	fIN = 50 Hz or 60 Hz	typ -120 dB	7
Signal-to-noise ratio SNR	fIN = 50 Hz or 60 Hz, gain = 1, VIN = –0.5 dBFS, normalized	typ 100 dB	7
Signal-to-noise ratio SNR	fIN = 50 Hz or 60 Hz, gain = 64, VIN = –0.5 dBFS, normalized	typ 79 dB	7
Total harmonic distortion THD	fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS	typ -100 dB	7
Spurious-free dynamic range SFDR	fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS	typ 105 dB	8
Internal reference voltage VREF		typ 1.2 V	8
Accuracy	Internal voltage reference; TA = 25°C; typical ±0.1%	typ 0.1 %	8
Temperature drift	Internal voltage reference	typ 7.5 · max 20 ppm/°C	8
Input current IIN	DGND < VDigital Input < DVDD	min -1 · max 1 uA	8
Analog supply current IAVDD	High-resolution mode	typ 3.5 · max 4 mA	8
Analog supply current IAVDD	Low-power mode	typ 2 · max 2.2 mA	8
Analog supply current IAVDD	Very-low-power mode	typ 1 · max 1.2 mA	8
Analog supply current IAVDD	Current-detect mode	typ 0.9 mA	8
Analog supply current IAVDD	Standby mode	typ 0.3 uA	8
Digital supply current(2) IDVDD	High-resolution mode; SPI idle	typ 0.4 · max 0.5 mA	8
Digital supply current(2) IDVDD	Low-power mode; SPI idle	typ 0.2 · max 0.3 mA	8
Digital supply current(2) IDVDD	Very-low-power mode; SPI idle	typ 0.1 · max 0.2 mA	8
Digital supply current(2) IDVDD	Current-detect mode; SPI idle	typ 0.065 mA	8
Digital supply current(2) IDVDD	Standby mode; SPI idle	typ 1 uA	8
Power dissipation PD	High-resolution mode	typ 12 mW	8
Power dissipation PD	Low-power mode	typ 6.6 mW	8
Power dissipation PD	Very-low-power mode	typ 3.3 mW	8
Power dissipation PD	Current-detect mode	typ 2.9 mW	8
Power dissipation PD	Standby mode	typ 3.9 uW	8
Pulse duration, CLKIN high tw(CLH)	1.65 V ≤ DVDD ≤ 2.0 V	min 49 ns	9
Pulse duration, CLKIN low tw(CLL)	1.65 V ≤ DVDD ≤ 2.0 V	min 49 ns	9
SCLK period tc(SC)	1.65 V ≤ DVDD ≤ 2.0 V	min 64 ns	9
Pulse duration, SCLK low tw(SCL)	1.65 V ≤ DVDD ≤ 2.0 V	min 32 ns	9
Pulse duration, SCLK high tw(SCH)	1.65 V ≤ DVDD ≤ 2.0 V	min 32 ns	9
Delay time, first SCLK rising edge after CS falling edge td(CSSC)	1.65 V ≤ DVDD ≤ 2.0 V	min 16 ns	9
Delay time, CS rising edge after final SCLK falling edge td(SCCS)	1.65 V ≤ DVDD ≤ 2.0 V	min 10 ns	9
Pulse duration, CS high tw(CSH)	1.65 V ≤ DVDD ≤ 2.0 V	min 20 ns	9
Setup time, DIN valid before SCLK falling egde tsu(DI)	1.65 V ≤ DVDD ≤ 2.0 V	min 5 ns	9
Hold time, DIN valid after SCLK falling edge th(DI)	1.65 V ≤ DVDD ≤ 2.0 V	min 8 ns	9
Pulse duration, SYNC/RESET low to generate device reset tw(RSL)	1.65 V ≤ DVDD ≤ 2.0 V	min 2048 tCLKIN	9
Pulse duration, SYNC/RESET low for synchronization tw(SYL)	1.65 V ≤ DVDD ≤ 2.0 V	min 1 · max 2047 tCLKIN	9
Setup time, SYNC/RESET valid before CLKIN rising edge tsu(SY)	1.65 V ≤ DVDD ≤ 2.0 V	min 10 ns	9
Pulse duration, CLKIN low tw(CLL)	2.7 V ≤ DVDD ≤ 3.6 V	min 49 ns	9
Pulse duration, CLKIN high tw(CLH)	2.7 V ≤ DVDD ≤ 3.6 V	min 49 ns	9
SCLK period tc(SC)	2.7 V ≤ DVDD ≤ 3.6 V	min 40 ns	9
Pulse duration, SCLK low tw(SCL)	2.7 V ≤ DVDD ≤ 3.6 V	min 20 ns	9
Pulse duration, SCLK high tw(SCH)	2.7 V ≤ DVDD ≤ 3.6 V	min 20 ns	9
Delay time, first SCLK rising edge after CS falling edge td(CSSC)	2.7 V ≤ DVDD ≤ 3.6 V	min 16 ns	9
Delay time, CS rising edge after final SCLK falling edge td(SCCS)	2.7 V ≤ DVDD ≤ 3.6 V	min 10 ns	9
Pulse duration, CS high tw(CSH)	2.7 V ≤ DVDD ≤ 3.6 V	min 15 ns	9
Setup time, DIN valid before SCLK falling egde tsu(DI)	2.7 V ≤ DVDD ≤ 3.6 V	min 5 ns	9
Hold time, DIN valid after SCLK falling edge th(DI)	2.7 V ≤ DVDD ≤ 3.6 V	min 8 ns	9
Pulse duration, SYNC/RESET low to generate device reset tw(RSL)	2.7 V ≤ DVDD ≤ 3.6 V	min 2048 tCLKIN	9
Pulse duration, SYNC/RESET low for synchronization tw(SYL)	2.7 V ≤ DVDD ≤ 3.6 V	min 1 · max 2047 tCLKIN	9
Setup time, SYNC/RESET valid before CLKIN rising edge tsu(SY)	2.7 V ≤ DVDD ≤ 3.6 V	min 10 ns	9
Propagation delay time, CS falling edge to DOUT driven tp(CSDO)	1.65 V ≤ DVDD ≤ 2.0 V; DOUT load: 20 pF \|\| 100 kΩ	max 50 ns	9
Progapation delay time, SCLK rising edge to valid new DOUT tp(SCDO)	1.65 V ≤ DVDD ≤ 2.0 V; DOUT load: 20 pF \|\| 100 kΩ	max 32 ns	9
Propagation delay time, CS rising edge to DOUT high impedance tp(CSDOZ)	1.65 V ≤ DVDD ≤ 2.0 V; DOUT load: 20 pF \|\| 100 kΩ	max 75 ns	9
Pulse duration, DRDY high tw(DRH)	1.65 V ≤ DVDD ≤ 2.0 V	typ 4 tCLKIN	9
Pulse duration, DRDY low tw(DRL)	1.65 V ≤ DVDD ≤ 2.0 V	typ 4 tCLKIN	9
SPI timeout	1.65 V ≤ DVDD ≤ 2.0 V	min 32768 tCLKIN	9
Power-on-reset time tPOR	1.65 V ≤ DVDD ≤ 2.0 V; measured from supplies at 90% to first DRDY rising edge	typ 250 us	9
Register default acquisition time tREGACQ	1.65 V ≤ DVDD ≤ 2.0 V	typ 5 us	9
Propagation delay time, CS falling edge to DOUT driven tp(CSDO)	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	max 50 ns	10
Progapation delay time, SCLK rising edge to valid new DOUT tp(SCDO)	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	max 20 ns	10
Propagation delay time, CS rising edge to DOUT high impedance tp(CSDOZ)	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	max 75 ns	10
Pulse duration, DRDY high tw(DRH)	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	typ 4 tCLKIN	10
Pulse duration, DRDY low tw(DRL)	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	typ 4 tCLKIN	10
SPI timeout	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	min 32768 tCLKIN	10
Power-on-reset time tPOR	Measured from supplies at 90% to first DRDY rising edge; 2.7 V ≤ DVDD ≤ 3.6 V	typ 250 us	10
Register default acquisition time tREGACQ	2.7 V ≤ DVDD ≤ 3.6 V; over operating ambient temperature range; DOUT load: 20 pF \|\| 100 kΩ	typ 5 us	10

Pins, by the datasheet

1 AVDD: Analog supply. Connect a 1-uF capacitor to AGND. · p. 4
2 AGND: Analog ground. · p. 4
3 AIN0P: Positive analog input 0. · p. 4
4 AIN0N: Negative analog input 0. · p. 4
5 AIN1N: Negative analog input 1. · p. 4
6 AIN1P: Positive analog input 1. · p. 4
7 AIN2P: Positive analog input 2. · p. 4
8 AIN2N: Negative analog input 2. · p. 4
9 AIN3N: Negative analog input 3. · p. 4
10 AIN3P: Positive analog input 3. · p. 4
11 SYNC/RESET: Conversion synchronization or system reset; active low. · p. 4
12 CS: Chip select; active low. · p. 4
13 DRDY: Data ready; active low. · p. 4
14 SCLK: Serial data clock. · p. 4
15 DOUT: Serial data output. · p. 4
16 DIN: Serial data input. · p. 4
17 CLKIN: Master clock input. · p. 4
18 CAP: Digital low-dropout (LDO) regulator output. Connect a 220-nF capacitor to DGND. · p. 4
19 DGND: Digital ground. · p. 4
20 DVDD: Digital I/O supply. Connect a 1-uF capacitor to DGND. · p. 4

Parameters

ADC architecture: Sigma-Delta
Clock Frequency: 8.192MHz
Clock/Oscillator: External
Current - Supply: 3.9mA
Current - Supply(Max): 4.5mA
Features: Built-in digital filter
Interface: SPI
Junction Temperature(Max): 150℃
Operating Temperature: -40℃~+125℃
Programmable Gain: Support
Quiescent Current (Iq): 4mA
Resolution (Bits): 24
Sampling Rate: 64kHz
Signal-to-Noise Ratio: 79dB
Standby Current: 1.3uA
Thermal Resistance(Junction to Ambient): 94.9℃/W
Thermal Resistance(Junction to Board): 46.4℃/W
Thermal Resistance(Junction to Case): 34.9℃/W
Voltage - Supply: 1.65V~3.6V
Voltage - Supply(Absolute Max): 3.9V
Voltage Reference: Built-in
differential input: Yes
number of channels: 4

Order codes

ADS131M04IPWTLCSC C2669857
ADS131M04IPWRLCSC C2862562

Pinout

The pins of the ADS131M04IPW
Pin	Name	Type
1	AVDD	Power in
2	AGND	Power in
3	AIN0P	Input
4	AIN0N	Input
5	AIN1N	Input
6	AIN1P	Input
7	AIN2P	Input
8	AIN2N	Input
9	AIN3N	Input
10	AIN3P	Input
11	SYNC/RESET	Input
12	CS	Input
13	DRDY	Output
14	SCLK	Input
15	DOUT	Tri-state
16	DIN	Input
17	CLKIN	Input
18	CAP	Passive
19	DGND	Power in
20	DVDD	Power in

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Parts like it

Questions

Is there a KiCad symbol and footprint for the ADS131M04IPW?

Yes. The symbol is Analog_ADC:ADS131M04xPW and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the ADS131M04IPW?

TSSOP-20, with 20 pins. Its footprint is drawn on this page.

Where is the ADS131M04IPW datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the ADS131M04IPW?

JLCPCB lists it as part C2862562, with 999 in stock; the sellers' links on this page open their listings.

What can replace the ADS131M04IPW?

Parts like it in the library: the ADS131M02IPW by Texas Instruments, the ADS131M03IPW by Texas Instruments, the ADS131M08IPBSR by Texas Instruments and the ADS131M02IRUK by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the ADS131M04IPW?

8 boards in 5 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

ADS131M04IPW

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

B091 2-4channel 24bit ADC ADS131M02-4

OLD ENGG3800-g15

Switching circuit v3

Device

Device

Device

Device

ENGG3800-g15

Parts like it

ADS131M02IPW

ADS131M03IPW

ADS131M08IPBSR

ADS131M02IRUK

ADS131M04IRUK

ADS131M08IPBS

MAX11270EUG+

AD7771BCPZ-RL

Questions

Is there a KiCad symbol and footprint for the ADS131M04IPW?

What package is the ADS131M04IPW?

Where is the ADS131M04IPW datasheet?

Where can I order the ADS131M04IPW?

What can replace the ADS131M04IPW?

Which open-source boards use the ADS131M04IPW?