USB5744/2G

Microchip Technology

0℃~+70℃ 1.2V、3.3V 5Gbps Hub USB 2.0、USB 3.2 VQFN-56-EP(7x7) USB HUB Controllers ROHS

Extended

Datasheetmicrochip/USB5744/2G

Category: USB Converters
Package: VQFN-56-EP(7x7)
Pins: 57

Overview

The USB5744/2G is a USB Converter made by Microchip Technology in a VQFN-56-EP(7x7) package with 57 pins. 0℃~+70℃ 1.2V、3.3V 5Gbps Hub USB 2.0、USB 3.2 VQFN-56-EP(7x7) USB HUB Controllers ROHS.

PCBKit's library has its KiCad symbol (Analog & Interface:USB5744, from CERN's library) and its footprint (ICs And Semiconductors SMD:QFN40P700X700X100-57N-S470, from CERN's library), ready for a KiCad board. 84 are in stock at JLCPCB (part C633619). 5 open-source boards in 4 repositories on GitHub use it.

Symbol

Analog & Interface:USB5744From CERN's library

Footprint

ICs And Semiconductors SMD:QFN40P700X700X100-57N-S470From CERN's library

From the datasheet

Supply, least: 1.08 V · VDD12, recommended operating min · p. 32
Supply, most: 1.32 V · VDD12, recommended operating max · p. 32
Supply, least: 3 V · VDD33, recommended operating min · p. 32
Supply, most: 3.6 V · VDD33, recommended operating max · p. 32
Supply, absolute maximum: 1.32 V · VDD12, absolute max · p. 32
Supply, absolute maximum: 4.6 V · VDD33, absolute max · p. 32
Works from: 0 °C · Commercial version, ambient min · p. 32
Works up to: 70 °C · Commercial version, ambient max · p. 32
Works from: -40 °C · Industrial version, ambient min · p. 32
Works up to: 85 °C · Industrial version, ambient max · p. 32
Junction, hottest: 125 °C · Junction temperature, absolute max · p. 32
Takes working: 781 mA · sum of VDD33 and VDD12, 4 SS/HS ports, typical · p. 34
Takes asleep: 2.6 mA · sum of VDD33 and VDD12, reset standby, typical · p. 34
Takes asleep: 7.2 mA · sum of VDD33 and VDD12, global suspend, typical · p. 34
Junction to air (56-VQFN): 30 K/W · Junction to ambient, air velocity 0 m/s · p. 33
Junction to air (56-VQFN): 26 K/W · Junction to ambient, air velocity 1 m/s · p. 33
Junction to case (56-VQFN): 2.6 K/W · Junction to case, air velocity 0 m/s · p. 33
Data rate, most: 5 Gbit/s · USB SuperSpeed max · p. 6
Takes at most: 781 mA · sum of VDD33 and VDD12, 4 SS/HS Ports, typical · p. 34

What it is and has

USB downstream ports: 4, USB 3.2 Gen 1 and USB 2.0 · p. 6
Microcontroller: On-chip · p. 1
RAM: 8 KB · p. 1
ROM: 64 KB · p. 1
OTP ROM: 8 KB · p. 1
Battery charging profiles: DCP · p. 6
Battery charging profiles: CDP, 1.5 A with data · p. 6
Battery charging profiles: SDP, 0.5 A with data · p. 6
Battery charging configuration: Custom profiles via SMBus or OTP · p. 6
Package: 56-pin VQFN, 7 x 7 mm · p. 1
ESD protection: 3 kV HBM JESD22-A114F · p. 1
VariSense: Programmable USB receiver sensitivity · p. 6
PHYBoost: Programmable Hi-Speed USB signal drive strength · p. 6
SPI ROM support: 1-bit and 2-bit SPI; 1 Mbit, 60 MHz or faster external ROM · p. 21
SPI modes: Mode 0 and mode 3 · p. 21
Controller: 4-Port SS/HS USB Controller Hub · p. 1
USB Link Power Management: Supported · p. 1
USB 2.0 pin tolerance: 5 V · p. 1
USB 3.2 Gen 1 pin tolerance: 1.32 V · p. 1
Integrated resistors: Termination and pull-up/pull-down resistors · p. 1
Package: 56-VQFN (7x7 mm) · p. 41

Around it

res 12.0 k (+/- 1%): between RBIAS and GND; Sets internal transceiver bias. · p. 14
res 10 k: between SPI_DO/SMDAT and pull-up supply; Pull-up selects SMBus slave mode together with the SPI_CLK pull-up; supply net is not specified on this page. · p. 16
res 50 k: between upstream VBUS and VBUS_DET; Upper resistor of the 50 kΩ / 100 kΩ divider that provides 3.3 V for a detachable hub. · p. 12
res 100 k: between VBUS_DET and GND; Lower resistor of the 50 kΩ / 100 kΩ divider that provides 3.3 V for a detachable hub. · p. 12
crystal 25MHz: between XTALI and XTALO; AT cut, fundamental, parallel resonant; use matching parallel load capacitors. · p. 39
cap matching parallel load capacitor: between XTALI and GND; Calculate the external capacitor using crystal load capacitance, pin capacitance and PCB capacitance; no external capacitor value is stated. · p. 39

Specifications

Parameter	Conditions	As printed	Page
+1.2 V Supply Voltage (VDD12) VDD12	Note 1	min -0.5 · max 1.32 V	32
+3.3 V Supply Voltage (VDD33) VDD33	Note 1	min -0.5 · max 4.6 V	32
Positive voltage on input signal pins, with respect to ground	Note 2; excludes USB DM/DP pins, XTAL1/CLK_IN, and XTALO	max 4.6 V	32
Negative voltage on input signal pins, with respect to ground		min -0.5 V	32
Positive voltage on XTALI/CLK_IN, with respect to ground		max 3.63 V	32
Positive voltage on USB DP/DM signal pins, with respect to ground		max 6 V	32
Positive voltage on USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground		max 1.32 V	32
Storage Temperature		min -55 · max 150 oC	32
Junction Temperature		max 125 oC	32
HBM ESD Performance		max 3 kV	32
+1.2 V Supply Voltage (VDD12) VDD12		min 1.08 · max 1.32 V	32
+3.3 V Supply Voltage (VDD33) VDD33		min 3 · max 3.6 V	32
Input Signal Pins Voltage	Note 2	min -0.3 · max 3.6 V	32
XTALI/CLK_IN Voltage		min -0.3 · max 3.6 V	32
USB 2.0 DP/DM Signal Pins Voltage		min -0.3 · max 5.5 V	32
USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage		min -0.3 · max 1.32 V	32
Ambient Operating Temperature in Still Air (TA) TA	Commercial version	min 0 · max 70 oC	32
Ambient Operating Temperature in Still Air (TA) TA	Industrial version	min -40 · max 85 oC	32
+1.2 V Supply Voltage Rise Time TRT	TRT in Figure 10-1	max 5 ms	32
+3.3 V Supply Voltage Rise Time TRT	TRT in Figure 10-1	max 5 ms	32
Junction to ambient thermal resistance JA	56-VQFN; velocity 0 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 30 °C/W	33
Junction to ambient thermal resistance JA	56-VQFN; velocity 1 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 26 °C/W	33
Junction to top thermal characterization parameter JT	56-VQFN; velocity 0 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 0.2 °C/W	33
Junction to top thermal characterization parameter JT	56-VQFN; velocity 1 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 0.3 °C/W	33
Junction to case thermal resistance JC	56-VQFN; velocity 0 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 2.6 °C/W	33
Junction to case thermal resistance JC	56-VQFN; velocity 1 Meters/s; multi-layer 2S2P PCB per JESDN51	typ 2.6 °C/W	33
PD(max) PD(max)		max 1400 mW	33
Reset	VDD33	typ 0.8 mA	34
Reset	VDD12	typ 1.8 mA	34
Reset	Typical Power	typ 4.8 mW	34
No VBUS	VDD33	typ 2 mA	34
No VBUS	VDD12	typ 5 mA	34
No VBUS	Typical Power	typ 12.6 mW	34
Global Suspend	VDD33	typ 2 mA	34
Global Suspend	VDD12	typ 5.2 mA	34
Global Suspend	Typical Power	typ 12.9 mW	34
4 FS Ports	VDD33	typ 39 mA	34
4 FS Ports	VDD12	typ 35 mA	34
4 FS Ports	Typical Power	typ 170 mW	34
4 HS Ports	VDD33	typ 53 mA	34
4 HS Ports	VDD12	typ 42 mA	34
4 HS Ports	Typical Power	typ 222 mW	34
4 SS Ports	VDD33	typ 55 mA	34
4 SS Ports	VDD12	typ 683 mA	34
4 SS Ports	Typical Power	typ 1001 mW	34
4 SS/HS Ports	VDD33	typ 93 mA	34
4 SS/HS Ports	VDD12	typ 688 mA	34
4 SS/HS Ports	Typical Power	typ 1132 mW	34
Low Input Level VIL	I Type Input Buffer	max 0.9 V	35
High Input Level VIH	I Type Input Buffer	min 2.1 V	35
Low Input Level VIL	IS Type Input Buffer	max 0.9 V	35
High Input Level VIH	IS Type Input Buffer	min 1.9 V	35
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	IS Type Input Buffer	min 9 · typ 20 · max 40 mV	35
Low Output Level VOL	O6 Type Output Buffer; IOL = 6 mA	max 0.4 V	35
Low Output Level VOL	O12 Type Output Buffer; IOL = 12 mA	max 0.4 V	35
Low Output Level VOL	OD12 Type Output Buffer; IOL = 12 mA	max 0.4 V	35
Low Input Level VIL	ICLK Type Input Buffer (XTALI Input)	max 0.5 V	35
High Input Level VIH	ICLK Type Input Buffer (XTALI Input); maximum is VDD33	min 0.85 V	35
VDD12 to VDD33 rise time tVDD33		min 0 ms	36
VDD33 to RESET_N/VBUS_DET rise time treset		min 0 ms	36
Configuration strap hold after external power supplies at operational levels tcsh	Power-on without RESET_N	min 1 ms	36
RESET_N input assertion time trstia		min 5 s	37
Configuration strap pins hold after RESET_N deassertion tcsh		min 1 ms	37
Clock frequency tfc	30 MHz operation	max 30 MHz	38
Chip enable (SPI_CE_EN) high time tceh	30 MHz operation	min 100 ns	38
Clock to input data tclq	30 MHz operation	max 13 ns	38
Input data hold time tdh	30 MHz operation	min 0 ns	38
Output setup time tos	30 MHz operation	min 5 ns	38
Output hold time toh	30 MHz operation	min 5 ns	38
Clock to output valid tov	30 MHz operation	min 4 ns	38
Chip enable (SPI_CE_EN) low to first clock tcel	30 MHz operation	min 12 ns	38
Last clock to chip enable (SPI_CE_EN) high tceh	30 MHz operation	min 12 ns	38
Clock frequency tfc	60 MHz operation	max 60 MHz	38
Chip enable (SPI_CE_EN) high time tceh	60 MHz operation	min 50 ns	38
Clock to input data tclq	60 MHz operation	max 9 ns	38
Input data hold time tdh	60 MHz operation	min 0 ns	38
Output setup time tos	60 MHz operation	min 5 ns	38
Output hold time toh	60 MHz operation	min 5 ns	38
Clock to output valid tov	60 MHz operation	min 4 ns	38
Chip enable (SPI_CE_EN) low to first clock tcel	60 MHz operation	min 12 ns	38
Last clock to chip enable (SPI_CE_EN) high tceh	60 MHz operation	min 12 ns	38
Frequency Ffund	Nominal	typ 25 MHz	39
Frequency Tolerance @ 25 oC Ftol	Maximum magnitude ±50 PPM; Note 6	max 50 PPM	39
Frequency Stability Over Temp Ftemp	Maximum magnitude ±50 PPM; Note 6	max 50 PPM	39
Total Allowable PPM Budget	Maximum magnitude ±100 PPM; Note 7	max 100 PPM	39
Shunt Capacitance CO		typ 7 pF	39
Load Capacitance CL		typ 20 pF	39
Drive Level PW		min 100 uW	39
Equivalent Series Resistance R1		max 50 Ω	39
XTALI/CLK_IN Pin Capacitance	Note 9; includes pad, bond wire and lead frame; excludes PCB capacitance	typ 3 pF	39
XTALO Pin Capacitance	Note 9; includes pad, bond wire and lead frame; excludes PCB capacitance	typ 3 pF	39
High Input Level VIH	ICLK Type Input Buffer (XTALI Input); maximum VDD33	min 0.85 V	35
Frequency Ffund		typ 25 MHz	39
Frequency Tolerance @ 25 oC Ftol	Maximum ±50 PPM; Note 6	max 50 PPM	39
Frequency Stability Over Temp Ftemp	Maximum ±50 PPM; Note 6	max 50 PPM	39
Total Allowable PPM Budget	Maximum ±100 PPM; Note 7	max 100 PPM	39
XTALI/CLK_IN Pin Capacitance	Note 9	typ 3 pF	39
XTALO Pin Capacitance	Note 9	typ 3 pF	39

Pins, by the datasheet

1 USB2DN_DP1/PRT_DIS_P1: USB 2.0 downstream port 1 D+; port disable configuration strap used with PRT_DIS_M1. · p. 8
2 USB2DN_DM1/PRT_DIS_M1: USB 2.0 downstream port 1 D-; port disable configuration strap used with PRT_DIS_P1. · p. 8
3 USB3DN_TXDP1: USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data plus; leave floating if unused. · p. 8
4 USB3DN_TXDM1: USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data minus; leave floating if unused. · p. 8
5 VDD12: +1.2 V core power. · p. 14
6 USB3DN_RXDP1: USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data plus; leave floating if unused. · p. 8
7 USB3DN_RXDM1: USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data minus; leave floating if unused. · p. 8
8 USB2DN_DP2/PRT_DIS_P2: USB 2.0 downstream port 2 D+; port disable configuration strap used with PRT_DIS_M2. · p. 8
9 USB2DN_DM2/PRT_DIS_M2: USB 2.0 downstream port 2 D-; port disable configuration strap used with PRT_DIS_P2. · p. 8
10 USB3DN_TXDP2: USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data plus; leave floating if unused. · p. 8
11 USB3DN_TXDM2: USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data minus; leave floating if unused. · p. 8
12 VDD12: +1.2 V core power. · p. 14
13 USB3DN_RXDP2: USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data plus; leave floating if unused. · p. 8
14 USB3DN_RXDM2: USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data minus; leave floating if unused. · p. 8
15 VDD12: +1.2 V core power. · p. 14
16 VDD33: +3.3 V power and internal regulator input. · p. 14
17 USB2DN_DP3/PRT_DIS_P3: USB 2.0 downstream port 3 D+; port disable configuration strap used with PRT_DIS_M3. · p. 8
18 USB2DN_DM3/PRT_DIS_M3: USB 2.0 downstream port 3 D-; port disable configuration strap used with PRT_DIS_P3. · p. 8
19 USB3DN_TXDP3: USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data plus; leave floating if unused. · p. 8
20 USB3DN_TXDM3: USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data minus; leave floating if unused. · p. 8
21 VDD12: +1.2 V core power. · p. 14
22 USB3DN_RXDP3: USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data plus; leave floating if unused. · p. 8
23 USB3DN_RXDM3: USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data minus; leave floating if unused. · p. 8
24 USB2DN_DP4/PRT_DIS_P4: USB 2.0 downstream port 4 D+; port disable configuration strap used with PRT_DIS_M4. · p. 8
25 USB2DN_DM4/PRT_DIS_M4: USB 2.0 downstream port 4 D-; port disable configuration strap used with PRT_DIS_P4. · p. 8
26 USB3DN_TXDP4: USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data plus; leave floating if unused. · p. 8
27 USB3DN_TXDM4: USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data minus; leave floating if unused. · p. 8
28 VDD12: +1.2 V core power. · p. 14
29 USB3DN_RXDP4: USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data plus; leave floating if unused. · p. 8
30 USB3DN_RXDM4: USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data minus; leave floating if unused. · p. 8
31 VDD33: +3.3 V power and internal regulator input. · p. 14
32 PRT_CTL4/GANG_PWR: Port 4 active-high power enable output and overcurrent sense input; pulled high enables gang mode; leave floating if unused. · p. 8
33 VDD12: +1.2 V core power. · p. 14
34 PRT_CTL3: Port 3 active-high power enable output and overcurrent sense input; leave floating if unused. · p. 12
35 PRT_CTL2: Port 2 active-high power enable output and overcurrent sense input; leave floating if unused. · p. 12
36 PRT_CTL1: Port 1 active-high power enable output and overcurrent sense input; leave floating if unused. · p. 12
37 VBUS_DET: Upstream bus power detection input; use a resistor divider to provide 3.3 V; alternate GPIO16. · p. 12
38 SPI_CLK/SMCLK: SPI clock in SPI mode; SMCLK in SMBus slave mode. · p. 8
39 SPI_DO/SMDAT: SPI data output in SPI mode; SMDAT in SMBus slave mode. · p. 8
40 SPI_DI/CFG_BC_EN: SPI data input in SPI mode; CFG_BC_EN in SMBus slave mode. · p. 8
41 SPI_CE_N/CFG_NON_REM: SPI chip enable in SPI mode; CFG_NON_REM in SMBus slave mode. · p. 8
42 RESET_N: Active-low input puts the device into Reset Mode. · p. 14
43 VDD12: +1.2 V core power. · p. 14
44 VDD33: +3.3 V power and internal regulator input. · p. 14
45 USB2UP_DP: USB 2.0 upstream data plus (D+). · p. 11
46 USB2UP_DM: USB 2.0 upstream data minus (D-). · p. 11
47 USB3UP_TXDP: USB 3.2 Gen 1 upstream SuperSpeed transmit data plus. · p. 11
48 USB3UP_TXDM: USB 3.2 Gen 1 upstream SuperSpeed transmit data minus. · p. 11
49 VDD12: +1.2 V core power. · p. 14
50 USB3UP_RXDP: USB 3.2 Gen 1 upstream SuperSpeed receive data plus. · p. 11
51 USB3UP_RXDM: USB 3.2 Gen 1 upstream SuperSpeed receive data minus. · p. 11
52 ATEST: Analog test pin; must always be connected to ground. · p. 14
53 XTALO: External 25 MHz crystal output; leave unconnected when using a single-ended external clock. · p. 14
54 XTALI/CLK_IN: External 25 MHz crystal input or single-ended reference clock input. · p. 8
55 VDD33: +3.3 V power and internal regulator input. · p. 14
56 RBIAS: Connect a 12.0 kΩ ±1% resistor to ground to set internal transceiver bias. · p. 14
Pad VSS: Common ground; connect exposed pad to the ground plane with a via array. · p. 14

Parameters

Current - Supply: 781mA
Current - Supply(Max): 781mA
Data Rate: 5000Mbps
Features: Low-power mode
Junction Temperature(Max): 125℃
Memory Interface: SMBus
Number of Channels: 4
Operating Temperature: -40℃~+85℃
Standby Current: 2.6mA
Thermal Resistance(Junction to Ambient): 30℃/W
Thermal Resistance(Junction to Case): 2.6℃/W
USB Protocol: USB 2.0
Voltage - Supply: 1.08V~3.6V
Voltage - Supply(Absolute Max): 1.32V
type: Hub

Order codes

USB5744/2GLCSC C633619

Pinout

The pins of the USB5744/2G
Pin	Name	Type
1	USB2DN_DP1/PRT_DIS_P1	Input/output
2	USB2DN_DM1/PRT_DIS_M1	Input/output
3	USB3DN_TXDP1	Input/output
4	USB3DN_TXDM1	Input/output
5	VDD12	Power in
6	USB3DN_RXDP1	Input/output
7	USB3DN_RXDM1	Input/output
8	USB2DN_DP2/PRT_DIS_P2	Input/output
9	USB2DN_DM2/PRT_DIS_M2	Input/output
10	USB3DN_TXDP2	Input/output
11	USB3DN_TXDM2	Input/output
12	VDD12	Power in
13	USB3DN_RXDP2	Input/output
14	USB3DN_RXDM2	Input/output
15	VDD12	Power in
16	VDD33	Power in
17	USB2DN_DP3/PRT_DIS_P3	Input/output
18	USB2DN_DM3/PRT_DIS_M3	Input/output
19	USB3DN_TXDP3	Input/output
20	USB3DN_TXDM3	Input/output
21	VDD12	Power in
22	USB3DN_RXDP3	Input/output
23	USB3DN_RXDM3	Input/output
24	USB2DN_DP4/PRT_DIS_P4	Input/output
25	USB2DN_DM4/PRT_DIS_M4	Input/output
26	USB3DN_TXDP4	Input/output
27	USB3DN_TXDM4	Input/output
28	VDD12	Power in
29	USB3DN_RXDP4	Input/output
30	USB3DN_RXDM4	Input/output
31	VDD33	Power in
32	PRT_CTL/GANG_PWR	Input
33	VDD12	Power in
34	PRT_CTL3	Input
35	PRT_CTL2	Input
36	PRT_CTL1	Input
37	VBUS_DET	Input/output
38	SPI_CLK/SMCLK	Input/output
39	SPI_DO/SMDAT	Input/output
40	SPI_DI/CFG_BC_EN	Input/output
41	SPI_CE_N/CFG_NON_REM	Input/output
42	RESET_N	Input
43	VDD12	Power in
44	VDD33	Power in
45	USB2UP_DP	Input
46	USB2UP_DM	Input
47	USB3UP_TXDP	Input
48	USB3UP_TXDM	Input
49	VDD12	Power in
50	USB3UP_RXDP	Input
51	USB3UP_RXDM	Input
52	ATEST	Input
53	XTALO	Input
54	XTALI/_CLK_IN	Input
55	VDD33	Power in
56	RBIAS	Input
57	EP_(VSS)	Power in

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Questions

Is there a KiCad symbol and footprint for the USB5744/2G?

Yes. The symbol is Analog & Interface:USB5744 and the footprint ICs And Semiconductors SMD:QFN40P700X700X100-57N-S470, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the USB5744/2G?

VQFN-56-EP(7x7), with 57 pins. Its footprint is drawn on this page.

Where is the USB5744/2G datasheet?

Microchip Technology publishes it: the Datasheet link on this page opens it.

Where can I order the USB5744/2G?

JLCPCB lists it as part C633619, with 84 in stock; the sellers' links on this page open their listings.

Which open-source boards use the USB5744/2G?

5 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.