4 layers125.7 × 76.5 mm
UGC Main R4K
HandHeldLegend/GC-Ultimate
The 3D shell, buttons, and other associated models are licensed under a Creative Commons Attribution 4.0 International License .
168 parts62
MCP3002-I/MS
Microchip TechnologyExtended
-40℃~+85℃ 10 1LSB 2 2.7V~5.5V 200kHz 5nA SAR SPI Yes MSOP-8 Analog to Digital Converters (ADC) ROHS
- Part id
- microchip/MCP3002-I/MS
- Category
- Analog To Digital Converters (ADC)
- Package
- MSOP-8
- Pins
- 8
- In stock
- 30 at JLCPCB (C635958)
- Used on
- 6 open-source boards
Overview
The MCP3002-I/MS is an analog To Digital Converter made by Microchip Technology in a MSOP-8 package with 8 pins. -40℃~+85℃ 10 1LSB 2 2.7V~5.5V 200kHz 5nA SAR SPI Yes MSOP-8 Analog to Digital Converters (ADC) ROHS.
PCBKit's library has its KiCad symbol (Analog_ADC:MCP3002, from KiCad's library) and its footprint (Package_SO:MSOP-8_3x3mm_P0.65mm, from KiCad's library), ready for a KiCad board. 30 are in stock at JLCPCB (part C635958). 6 open-source boards in 3 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
9- Supply, least
- 2.7 V · VDD, recommended operating min · p. 3
- Supply, most
- 5.5 V · VDD, recommended operating max · p. 3
- Supply, absolute maximum
- 7 V · VDD, absolute max · p. 2
- Works from
- -40 °C · Operating ambient temperature min · p. 4
- Works up to
- 85 °C · Operating ambient temperature max · p. 4
- Takes working
- 525 µA · VDD, typical operating current at 5 V, 200 ksps, DOUT unloaded · p. 3
- Takes at most
- 650 µA · VDD, max operating current at 5 V, DOUT unloaded · p. 3
- Takes asleep
- 5 nA · VDD, typical standby current, CS = VDD = 5 V · p. 3
- Junction to air (8L-MSOP)
- 211 K/W · Typical junction-to-ambient thermal resistance · p. 4
What it is and has
7- ADC resolution
- 10-bit · p. 1
- Analog inputs
- Two single-ended channels or one pseudo-differential pair · p. 1
- Sample and hold
- On-chip · p. 1
- Serial interface
- SPI, modes 0,0 and 1,1 · p. 1
- Maximum sampling rate
- 200 ksps at VDD = 5V · p. 1
- Maximum sampling rate
- 75 ksps at VDD = 2.7V · p. 1
- Package options
- 8-pin MSOP, PDIP, SOIC and TSSOP · p. 1
Specifications
46| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| VDD VDD | max 7 V | 2 | |
| All Inputs and Outputs w.r.t. VSS | Maximum: VDD + 0.6V | min -0.6 V | 2 |
| Storage Temperature | min -65 · max 150 °C | 2 | |
| Ambient temperature with power applied | min -65 · max 150 °C | 2 | |
| Conversion Time TCONV | max 10 clock cycles | 2 | |
| Analog Input Sample Time TSAMPLE | typ 1.5 clock cycles | 2 | |
| Throughput Rate FSAMPLE | VDD = 5V | max 200 ksps | 2 |
| Throughput Rate FSAMPLE | VDD = 2.7V | max 75 ksps | 2 |
| Resolution | typ 10 bits | 2 | |
| Integral Nonlinearity INL | Typical and maximum values are ± magnitudes | typ 0.5 · max 1 LSB | 2 |
| Differential Nonlinearity DNL | No missing codes over temperature; typical and maximum values are ± magnitudes | typ 0.25 · max 1 LSB | 2 |
| Offset Error | Maximum is ± magnitude | max 1.5 LSB | 2 |
| Gain Error | Maximum is ± magnitude | max 1 LSB | 2 |
| Total Harmonic Distortion THD | VIN = 0.1V to 4.9V@1 kHz | typ -76 dB | 2 |
| Signal to Noise and Distortion (SINAD) SINAD | VIN = 0.1V to 4.9V@1 kHz | typ 61 dB | 2 |
| Spurious Free Dynamic Range SFDR | VIN = 0.1V to 4.9V@1 kHz | typ 78 dB | 2 |
| Leakage Current | Maximum is ± magnitude | typ 0.001 · max 1 uA | 2 |
| Sample Capacitor CSAMPLE | See Figure 4-1 | typ 20 pF | 2 |
| High Level Output Voltage VOH | IOH = -1 mA, VDD = 4.5V | min 4.1 V | 3 |
| Low Level Output Voltage VOL | IOL = 1 mA, VDD = 4.5V | max 0.4 V | 3 |
| Input Leakage Current ILI | VIN = VSS or VDD | min -10 · max 10 uA | 3 |
| Output Leakage Current ILO | VOUT = VSS or VDD | min -10 · max 10 uA | 3 |
| Pin Capacitance (All Inputs/Outputs) CIN, COUT | VDD = 5.0V; TA = 25°C, f = 1 MHz; Note 1 | max 10 pF | 3 |
| Clock Frequency fCLK | VDD = 5V; Note 2 | max 3.2 MHz | 3 |
| Clock Frequency fCLK | VDD = 2.7V; Note 2 | max 1.2 MHz | 3 |
| Clock High Time tHI | min 140 ns | 3 | |
| Clock Low Time tLO | min 140 ns | 3 | |
| CS Fall To First Rising CLK Edge tSUCS | min 100 ns | 3 | |
| Data Input Setup Time tSU | min 50 ns | 3 | |
| Data Input Hold Time tHD | min 50 ns | 3 | |
| CLK Fall To Output Data Valid tDO | VDD = 5V, see Figure 1-2 | max 125 ns | 3 |
| CLK Fall To Output Data Valid tDO | VDD = 2.7V, see Figure 1-2 | max 200 ns | 3 |
| CLK Fall To Output Enable tEN | VDD = 5V, see Figure 1-2 | max 125 ns | 3 |
| CLK Fall To Output Enable tEN | VDD = 2.7V, see Figure 1-2 | max 200 ns | 3 |
| CS Rise To Output Disable tDIS | See Test Circuits, Figure 1-2; Note 1 | max 100 ns | 3 |
| CS Disable Time tCSH | min 310 ns | 3 | |
| DOUT Rise Time tR | See Test Circuits, Figure 1-2; Note 1 | max 100 ns | 3 |
| DOUT Fall Time tF | See Test Circuits, Figure 1-2; Note 1 | max 100 ns | 3 |
| Operating Voltage VDD | min 2.7 · max 5.5 V | 3 | |
| Operating Current IDD | VDD = 5.0V, DOUT unloaded; fSAMPLE = 200 ksps, fCLK = 16*fSAMPLE | typ 525 · max 650 uA | 3 |
| Operating Current IDD | VDD = 2.7V, DOUT unloaded | typ 300 uA | 3 |
| Standby Current IDDS | CS = VDD = 5.0V | typ 0.005 · max 2 uA | 3 |
| Specified Temperature Range TA | VDD = +2.7V to +5.5V, VSS = GND | min -40 · max 85 °C | 4 |
| Operating Temperature Range TA | VDD = +2.7V to +5.5V, VSS = GND | min -40 · max 85 °C | 4 |
| Storage Temperature Range TA | min -65 · max 150 °C | 4 | |
| Thermal Resistance, 8L-MSOP JA | 8L-MSOP | typ 211 °C/W | 4 |
Pins, by the datasheet
8- 1 CS/SHDN
- Chip Select/Shutdown Input; pull low to communicate and high between conversions for standby. · p. 12
- 2 CH0
- Channel 0 Analog Input; programmable for single-ended or pseudo-differential operation. · p. 12
- 3 CH1
- Channel 1 Analog Input; programmable for single-ended or pseudo-differential operation. · p. 12
- 4 VSS
- Ground. · p. 12
- 5 DIN
- Serial Data In; clocks in input channel configuration data. · p. 12
- 6 DOUT
- Serial Data Out; shifts out conversion results, changing on falling clock edges. · p. 12
- 7 CLK
- Serial Clock; initiates conversion and clocks out conversion bits. · p. 12
- 8 VDD/VREF
- +2.7V to 5.5V Power Supply and Reference Voltage Input. · p. 12
Open-source boards using it
6- 4 layers110.9 × 59.7 mm
- 4 layers125.7 × 65.9 mm
UGC OpenMain
HandHeldLegend/Open-GC-Ultimate
Fully open, bare-bones GC Ultimate PCB made for makers and indies.
117 parts3AGPL-3.0 - 4 layers125.7 × 76.5 mm
UGC Main
HandHeldLegend/GC-Ultimate
The 3D shell, buttons, and other associated models are licensed under a Creative Commons Attribution 4.0 International License .
128 parts62 - 4 layers110.9 × 59.7 mm
- 4 layers110.9 × 59.7 mm
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Questions
Is there a KiCad symbol and footprint for the MCP3002-I/MS?
Yes. The symbol is Analog_ADC:MCP3002 and the footprint Package_SO:MSOP-8_3x3mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the MCP3002-I/MS?
MSOP-8, with 8 pins. Its footprint is drawn on this page.
Where is the MCP3002-I/MS datasheet?
Microchip Technology publishes it: the Datasheet link on this page opens it.
Where can I order the MCP3002-I/MS?
JLCPCB lists it as part C635958, with 30 in stock; the sellers' links on this page open their listings.
What can replace the MCP3002-I/MS?
Parts like it in the library: the AD7276ARMZ-REEL by Analog Devices, the AD7683BRMZRL7 by Analog Devices, the ADS8326IDGK by Texas Instruments and the MCP3551-E/MS by Microchip Technology. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the MCP3002-I/MS?
6 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.