

TLS115D0EJ
Infineon Technologies
-40℃~+150℃@(Tj) 1 150mA 2V~14V 45V 500mV@(150mA) 85dB@(100Hz) 90uA Adjustable Over Current Protection、Short Circuit Protection、Thermal shutdown、Enable control、Operating status indication、Reverse polarity voltage protection、Built-in soft-start Positive DSO-8 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS
- Category
- Voltage Regulators Linear, Low Drop Out (LDO) Regulators
- Package
- DSO-8
- Pins
- 9
Overview
The TLS115D0EJ is a voltage Regulators Linear, Low Drop Out (LDO) Regulator made by Infineon Technologies in a DSO-8 package with 9 pins. -40℃~+150℃@(Tj) 1 150mA 2V~14V 45V 500mV@(150mA) 85dB@(100Hz) 90uA Adjustable Over Current Protection、Short Circuit Protection、Thermal shutdown、Enable control、Operating status indication、Reverse polarity voltage protection、Built-in soft-start Positive DSO-8 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:TLS115D0EJXUMA1, from EasyEDA) and its footprint (EasyEDA_Cloud:ESOP-8_L4.9-W3.9-P1.27-LS6.0-BL-EP, from EasyEDA), ready for a KiCad board. 4,677 are in stock at JLCPCB (part C3747428). 2 open-source boards in 2 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
15- Supply, least
- 4 V · IN, functional range minimum · p. 8
- Supply, most
- 45 V · IN, functional range maximum · p. 8
- Supply, absolute maximum
- 45 V · IN, absolute maximum · p. 7
- Junction, hottest
- 150 °C · Junction temperature maximum · p. 7
- Takes working
- 55 µA · IN, typical quiescent current, IOUT ≤ 0.1 mA, VADJ = 5 V, Tj ≤ 125 °C · p. 16
- Takes working
- 7 mA · IN, typical quiescent current, IOUT ≤ 150 mA, VADJ = 5 V · p. 16
- Takes asleep
- 100 nA · IN, typical standby current, VEN ≤ 0.4 V, Tj ≤ 125°C · p. 16
- Gives
- 150 mA · OUT, rated output current capability · p. 1
- Current limit
- 350 mA · Typical output current limitation, VOUT = VADJ - 0.1 V, VADJ = 5 V · p. 11
- Dropout
- 250 mV · Typical dropout at IOUT = 150 mA, VADJ = 5 V · p. 11
- Junction to case (PG-DSO-8)
- 18 K/W · Typical junction to case · p. 8
- Junction to air (PG-DSO-8)
- 50 K/W · Typical junction to ambient, 2s2p board · p. 8
- Junction to air (PG-DSO-8)
- 157 K/W · Typical junction to ambient, 1s0p board, footprint only · p. 8
- Junction to air (PG-DSO-8)
- 77 K/W · Typical junction to ambient, 1s0p board, 300 mm2 heatsink area · p. 8
- Junction to air (PG-DSO-8)
- 63 K/W · Typical junction to ambient, 1s0p board, 600 mm2 heatsink area · p. 8
What it is and has
11- Output current capability
- 150 mA · p. 1
- Output voltage
- Adjustable down to 2.0 V · p. 1
- Output capacitor compatibility
- Stable with ceramic output capacitors · p. 1
- Power good
- Overvoltage and undervoltage indication · p. 1
- Soft start
- Internally controlled · p. 1
- Protection
- Output short circuit to GND and battery · p. 1
- Protection
- Reverse polarity protected input · p. 1
- Protection
- Overtemperature protection · p. 1
- Compliance
- RoHS compliant · p. 1
- Qualification
- Automotive applications; product validation according to AEC-Q100 · p. 1
- Package
- PG-DSO-8 · p. 1
Around it
4- cap 100 nF to 470 nF
- between IN and GND; CIN1 ceramic capacitor; filters high frequency disturbance. Place as close as possible to the input pin. · p. 24
- cap 10 µF to 470 µF
- between IN and GND; CIN2 aluminum electrolytic capacitor; smoothens high energy pulses. Place close to the input pin. · p. 24
- cap 1 µF minimum
- between OUT and GND; COUT required for stability; ESR maximum 5 Ω. Minimum capacitance requirement applies for a worst case capacitance tolerance of 30%. X5R or X7R ceramic recommended in automotive applications; place close to OUT and GND on the same PCB side as the device. · p. 8
- res Sized depending on pull-up voltage
- between PG and positive voltage rail; Required pull-up resistor; maintain PG absolute maximum ratings and limit external input current. The application example uses microcontroller VDD. · p. 25
Specifications
44| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Voltage VIN | Input IN | min -16 · max 45 V | 7 |
| Voltage VEN | Enable EN | min -16 · max 45 V | 7 |
| Voltage VADJ | Adjust ADJ | min -16 · max 45 V | 7 |
| Voltage VOUT | Output OUT | min -5 · max 45 V | 7 |
| Voltage VIN - VOUT | Input output voltage difference | min -30 · max 45 V | 7 |
| Voltage VPG | Power good PG | min -0.3 · max 7 V | 7 |
| Junction temperature Tj | min -40 · max 150 °C | 7 | |
| Storage temperature Tstg | min -55 · max 150 °C | 7 | |
| ESD susceptibility to GND VESD,HBM | Human Body Model (HBM); not subject to production test, specified by design | min -4 · max 4 kV | 7 |
| ESD susceptibility to GND VESD,CDM | Charged Device Model (CDM); not subject to production test, specified by design | min -1 · max 1 kV | 7 |
| ESD susceptibility to GND VESD,CDM | Charged Device Model (CDM) at corner pins; not subject to production test, specified by design | min -1 · max 1 kV | 7 |
| Input voltage range VIN | min 4 · max 45 V | 8 | |
| Adjust input voltage range (voltage tracking range) VADJ | min 2 · max 14 V | 8 | |
| Capacitance of output capacitor COUT | Minimum requirement applies for a worst case capacitance tolerance of 30%; not subject to production test, specified by design | min 1 uF | 8 |
| Equivalent series resistance of output capacitor ESRCOUT | Not subject to production test, specified by design | max 5 Ω | 8 |
| Junction temperature Tj | min -40 · max 150 °C | 8 | |
| Junction to case RthJC | PG-DSO-8; not subject to production test, specified by design | typ 18 K/W | 8 |
| Junction to pin RthJP | PG-DSO-8 | typ 85 K/W | 8 |
| Junction to ambient RthJA | PG-DSO-8; 2s2p board | typ 50 K/W | 8 |
| Junction to ambient RthJA | PG-DSO-8; 1s0p board, footprint only | typ 157 K/W | 8 |
| Junction to ambient RthJA | PG-DSO-8; 1s0p board, 300 mm2 heatsink area on PCB | typ 77 K/W | 8 |
| Junction to ambient RthJA | PG-DSO-8; 1s0p board, 600 mm2 heatsink area on PCB | typ 63 K/W | 8 |
| Output voltage tracking accuracy ∆VOUT | ∆VOUT = VADJ - VOUT; 5.5 V ≤ VIN ≤ 22 V; 0.1 mA ≤ IOUT ≤ 150 mA; 2 V ≤ VADJ ≤ VIN - 1 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min -5 · max 5 mV | 11 |
| Output voltage tracking accuracy ∆VOUT | ∆VOUT = VADJ - VOUT; 5.5 V ≤ VIN ≤ 32 V; 0.1 mA ≤ IOUT ≤ 70 mA; 2 V ≤ VADJ ≤ VIN - 1 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min -5 · max 5 mV | 11 |
| Load regulation steady-state ∆VOUT,load | VIN = 13.5 V; IOUT = 0.1 mA to 150 mA; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min -4 · typ -0.1 mV | 11 |
| Line regulation steady-state ∆VOUT,line | VIN = 5.5 V to 32 V; IOUT = 10 mA; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | typ 0.1 · max 4 mV | 11 |
| Power supply ripple rejection PSRR | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; fripple = 100 Hz; Vripple = 1 Vpp; IOUT = 10 mA; COUT = 10 uF, ceramic type; not subject to production test, specified by design | typ 85 dB | 11 |
| Output current limitation IOUT,max | VIN = 13.5 V; VOUT = VADJ - 0.1 V; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min 151 · typ 350 · max 500 mA | 11 |
| Reverse current IOUT,rev | VIN = 0 V; VOUT = 16 V; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min -3.5 · typ -1.7 mA | 11 |
| Reverse current at negative input voltage IIN,rev | VIN = -16 V; VOUT = 0 V; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min -4 · typ -2 mA | 11 |
| Dropout voltage Vdr | Vdr = VIN - VOUT; IOUT = 150 mA; VADJ = 5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; measured when VOUT has dropped 100 mV from the nominal value obtained at VIN = 13.5 V | typ 250 · max 500 mV | 11 |
| Overtemperature shutdown threshold Tj,sd | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj increasing due to power dissipation generated by the device | typ 175 °C | 12 |
| Overtemperature shutdown threshold hysteresis ∆Tj,sdh | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V | typ 15 K | 12 |
| Current consumption stand-by mode Iq,off | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; Iq,off = IIN; VEN ≤ 0.4 V; -40°C ≤ Tj ≤ 125°C | typ 0.1 · max 5 uA | 16 |
| Current consumption Iq | VIN = 13.5 V; VEN ≥ 2.0 V; Iq = IIN - IOUT; IOUT ≤ 0.1 mA; VADJ = 5 V; -40°C ≤ Tj ≤ 125 °C | typ 55 · max 90 uA | 16 |
| Current consumption Iq | VIN = 13.5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; Iq = IIN - IOUT; IOUT ≤ 150 mA; VADJ = 5 V | typ 7 · max 14 mA | 16 |
| Enable off voltage range VEN,off | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VOUT = 0 V; IOUT ≤ 5 uA; -40°C ≤ Tj ≤ 125°C | max 0.8 V | 19 |
| Enable on voltage range VEN,on | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; Tj = -40°C to 150°C; VOUT settled | min 2 V | 19 |
| Enable input current IEN | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; Tj = -40°C to 150°C; VEN = 5 V | typ 2 · max 4 uA | 19 |
| Adjust input current IADJ | VIN = 13.5 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; VADJ = 5 V | typ 0.03 · max 1 uA | 21 |
| Power good reaction time tPG,r | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C | min 10 · typ 15 · max 30 us | 23 |
| Power good output "low" voltage VPG,low | VIN ≥ 4 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; IPG,ext ≤ 1.8 mA | typ 0.2 · max 0.4 V | 23 |
| Power good output external input current IPG,ext | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; VPG ≤ 0.4 V | max 1.8 mA | 23 |
| Power good output leakage current IPG,leak | VIN = 13.5 V; 2.0 V ≤ VADJ ≤ 14 V; VEN ≥ 2.0 V; Tj = -40°C to 150°C; VOUT = VADJ; VPG = 5 V | typ 0 · max 2 uA | 23 |
Pins, by the datasheet
9- 1 OUT
- Tracker output with 150 mA capability; connect a capacitor to GND close to the pins, meeting Table 2 capacitance and ESR requirements. · p. 6
- 2 N.C.
- Not connected. · p. 6
- 3 GND
- Ground. · p. 6
- 4 PG
- Power good output; connect to a positive voltage rail through a pull-up resistor. Low indicates a tracker output fault. · p. 6
- 5 ADJ
- Adjust input; connect to the reference voltage. · p. 6
- 6 N.C.
- Not connected. · p. 6
- 7 EN
- High enables the tracker; low disables it. Connect EN to IN if the enable function is not required. · p. 6
- 8 IN
- Input; a small ceramic capacitor to GND close to the pins is recommended to compensate line influence. · p. 6
- Pad –
- Exposed pad; connect to GND. Connection to a heat sink is recommended. · p. 6
Parameters
16- Current Limit
- 350mA
- Features
- Enable control
- Junction Temperature(Max)
- 150℃
- Number of Outputs
- 1
- Operating Temperature
- -40℃~+150℃@(Tj)
- Output Configuration
- Positive
- Output Current
- 150mA
- Output Type
- Adjustable
- Output Voltage
- 2V~14V
- Power Supply Rejection Ratio (PSRR)
- 85dB@(100Hz)
- Standby Current
- 100nA
- Thermal Resistance(Junction to Ambient)
- 157℃/W
- Thermal Resistance(Junction to Case)
- 18℃/W
- Voltage - Supply
- 4V~45V
- Voltage - Supply(Absolute Max)
- 45V
- Voltage Dropout
- 250mV
Order codes
2- TLS115D0EJLCSC C3747428
- TLS115D0EJLCSC C540242
Pinout
9| Pin | Name | Type |
|---|---|---|
| 1 | OUT | Unspecified |
| 2 | N.C. | Unspecified |
| 3 | GND | Unspecified |
| 4 | PG | Unspecified |
| 5 | ADJ | Unspecified |
| 6 | N.C. | Unspecified |
| 7 | EN | Unspecified |
| 8 | IN | Unspecified |
| 9 | EP | Unspecified |
Open-source boards using it
All 2- 4 layers103 × 82.4 mm

- 4 layers162 × 115 mm

Fome mc
halbritt/fome-mc
FOME-MC integrated single-PCB motorcycle ECU (STM32H753 + 2x STM32F042 WBO)
514 parts1
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Is there a KiCad symbol and footprint for the TLS115D0EJ?
Yes. The symbol is EasyEDA_Cloud:TLS115D0EJXUMA1 and the footprint EasyEDA_Cloud:ESOP-8_L4.9-W3.9-P1.27-LS6.0-BL-EP, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the TLS115D0EJ?
DSO-8, with 9 pins. Its footprint is drawn on this page.
Where is the TLS115D0EJ datasheet?
Infineon Technologies publishes it: the Datasheet link on this page opens it.
Where can I order the TLS115D0EJ?
JLCPCB lists it as part C3747428, with 4,677 in stock; the sellers' links on this page open their listings.
What can replace the TLS115D0EJ?
Parts like it in the library: the RT9048GSP by Richtek Tech, the BL1118CS8TR1833 by BL, the MD7672B50SF4 by Shanghai Mingda Microelectronics and the MD85E50SF4 by Shanghai Mingda Microelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the TLS115D0EJ?
2 boards in 2 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
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