Ntsc syncgen

NTSC framebuffer built around 74x cmos logic gates and an 128k x 8bit sram module

** this is incomplete and not yet built, in-progress **

• 8 bits for color + brightness
• 17 bits address
• transfer data in during vblank period

Tasks remaining:

• complete memory addressing circuitry
• check gate timings for brightness & color control paths
• place adjustment potentiometers for setting PNP transistor bias
• distribute ceramic capacitors
• add debug testpads onto pcb

Table of Contents

• Current PCB Layout
• H&V Counter
• HRESET
• VRESET
• HBLANK
• VBLANK
• COLORBURST
• COLORSELECT
• BRIGHTNESS
• MEMORYANDBUS
• Output Amplifier
• Components selection
• Simulating

Current PCB Layout

hvcounter

This is the core of the circuit, its two 4040 counters, one driving the other. the first counts out 454 which is the number of inactive + active horizontal pixels per row. the output is binary, and with enough AND gates alongside numerous D type flipflops, specific events can be timed out and set to form the sync timings needed

HRESET

256 + 128 + 64 + 4 + 2 counts out 454 horizontal & sets HRESET flag to high 5V and on the next clock pulse from not the timer we are resetting but the actual clock source

VRESET

vreset is 1V + 4V + 256V for 261 vertical lines before resetting the counter

vertical reset is checked at the end of the horizontal scanline, so we use _HRESET as the clock for vreset - the condition of 261V lines is set only when _HRESET is ready

HBLANK-HSYNC

the circuit starts off with some DC bias to give a sync tip from the "previous" scanline, and then at H2 + H8 HBLANK-ENABLE flop is cycled on. When this is on, elsewhere in the circuit the bias is cut off and gives us the horizontal sync tip

When H2 + H8 + H32 is seen (H42) , HBLANK_DISABLE is turned on, which is a 2nd flop "HSYNC B"

this lets me chain the hsync events together with explicit start and stop events, block them from re-triggering

VBLANK-VSYNC

COLORBURST

COLORSELECT

the 4-16 mux is often used for memory addressing and is only available in active-low, so in this case im using NOR gates to invert the signal . the MUX outputs are always high-inactive, so all NOR gates except for the active one are getting a positive voltage which turns them all off, exxcept for the active-low received from the MUX, this NOR gate switches on and provides a color clock at specific delays introduced by the 74AHC451's 4-5ns gate propigation delay

BRIGHTNESS

MEMORYANDBUS

outputamp

The output-amplifier interfaces the low-current, low impedience CMOS or TTL logic with the 1.4v, 75-ohm composite.

HSYNC, Colorburst, and Pixel Input are given to the amplifiers input. Its first passed through a 2n7000 N-channel mosfet which inverts the signal. This drives a PNP transistor to return it back to positive output, this allowed the GND of the composite-out to also be the same reference plane as the GND of this circuit (pnp could be omitted and use only mosfet with resistor network and floating Gnd)

This has two additional mosfets for saturation bias and output voltage reduction (brightness). The saturation mosfet biases the PNPs turnoff point "upwards" so that its off point rises above what hsync/hblank would have been . this serves the purpose of adding DC bias to reduce the modulation of the output without affecting the output peak (overall brightness). in summary, this is an amplifier which can control the height of the bottoms and tops of the wave output separately. its needed for color, but could dispose of half the mosfets if it were used for monochrome

Components

• 74HC74 D-FLOP
• 74HC08 AND
• 74HC02 NOR
• 74hc244 buffers
• 74hc154 4-to-16 mux
• 74ahc541 inv buffers (color delay line)
• CD4040 12 bit counter
• 14.318mhz crystal
• 128x8 sram HM628128DLP-5
• 2n5087 pnp or equivalent
• 2n7000 mosfet
• 7805 regulator

simtools

LTSpice Model of Output Amplifier

Digital Logic simulation

output amplifier in ltspice, showing peak brightness vs minimum brightness pixels , there is some distortion in the sim. Some gates are switching on/off before others and causing brief voltage spikes, this might be ignorable on the physical circuit ill have to go through the circuit flow to see what the issue is