ADE9000 Breakout

ADE9000 Breakout Board

Breadboard-compatible breakout for the Analog Devices ADE9000 — a high-performance, multiphase energy and power quality monitoring IC.

The board follows the test circuit from Figure 55 of the ADE9000 datasheet (Rev. B, p. 28): all onboard passives (decoupling, RC anti-aliasing filters, crystal load caps, reset RC) are populated, power plus the analog channels are broken out to 0.1" headers, and the remaining digital signals are exposed on test pads to keep the board compact.

3D renders

These views are rendered from the populated KiCad assembly using the project-local STEP models.

Top isometric	Bottom isometric

Features

• ADE9000 in 40-lead LFCSP (CP-40-7) package
• 3.3 V single-supply operation
• Onboard 24.576 MHz crystal with 16 pF load caps (CLKIN/CLKOUT)
• Onboard RC anti-aliasing filters on all 7 analog input pairs (1 kΩ + 22 nF)
• Onboard reset RC (10 kΩ pull-up + 1 µF)
• Onboard decoupling on VDD, AVDDOUT, DVDDOUT, and REF per datasheet
• CF2 activity LED with 1 kΩ current-limit resistor
• Power plus analog inputs broken out to 0.1" headers
• SPI, CF, IRQ, CLK, and RESET exposed on test pads
• ATM90E36-style three-pad solder bridges for manual PM0/PM1 mode selection

Pin Headers

J1 — Power

J2 — Current Inputs (left side, top)

Each input pair has a 1 kΩ series resistor and 22 nF cap to GND already fitted on board. Max differential input ±1 V / PGA gain.

J3 — Voltage Inputs (left side, bottom)

Each input pair has the same 1 kΩ + 22 nF RC filter as the current inputs.

Test Pads — Digital I/O

Power

• Supply 3.3 V into the J1 3.3V pin (or the dedicated 3V3 pad).
• Current draw: ~15–17 mA in normal mode (PSM0).
• Onboard decoupling (per datasheet §Test Circuit):
  • VDD (pin 27): 10 µF + 0.1 µF ceramic to GND
  • AVDDOUT (pin 25): 4.7 µF + 0.1 µF ceramic to GND — do not drive externally
  • DVDDOUT (pin 3): 4.7 µF + 0.1 µF ceramic to GND — do not drive externally
  • REF (pin 16): 4.7 µF + 0.1 µF ceramic to REFGND (internal 1.25 V reference)

PM0/PM1 mode bridges

JP1 controls PM0 and JP2 controls PM1. Each open three-pad jumper is marked 1 PMx 0: bridge the center pad to 1 for +3V3, or to 0 for GND.

Bridge exactly one side of each jumper before powering the board. Never bridge both sides, and do not leave a mode pin floating. Production boards intended for normal operation should have the 0 side bridged on both JP1 and JP2.

Clock

A 24.576 MHz crystal is fitted between CLKIN (pin 29) and CLKOUT (pin 30) with 16 pF load capacitors to GND. This matches the ADE9000's required ±30 ppm clock.

To use an external clock instead, remove the crystal, leave the load caps unpopulated, and drive CLKIN directly (3.3 V logic, 24.330–24.822 MHz, 45:55–55:45 duty cycle).

SPI Interface

The ADE9000 uses SPI mode 0 (CPOL=0, CPHA=0), MSB first, up to 20 MHz.

All SPI pins are 3.3 V logic. Use a level shifter if connecting to a 5 V MCU.

Analog Input Signal Conditioning

The onboard RC filter on each analog input pin:

Signal ──[ 1 kΩ ]──┬── IxP / VxP (ADE9000 pin)
                   │
                 [22 nF]
                   │
                  GND

This provides a first-order anti-aliasing LPF with fc ≈ 7.2 kHz, matching the ADC's −3 dB bandwidth. For CT or Rogowski coil inputs, drive the differential pair through an additional burden resistor or signal conditioning stage before these onboard filters.

BOM Summary

Source purchasing fields live on the schematic symbols as Manufacturer, MPN, DigiKey, Mouser, and Description properties. Regenerate the grouped purchasing BOM with:

& "C:\Program Files\KiCad\10.0\bin\python.exe" .\scripts\apply_bom_fields.py
& "C:\Program Files\KiCad\10.0\bin\python.exe" .\scripts\export_bom.py --html .\bom\ADE9000_Breakout_BOM.html

Generated outputs are available as bom/ADE9000_Breakout_BOM.csv, bom/ADE9000_Breakout_BOM.xlsx, and bom/ADE9000_Breakout_BOM.html. The DigiKey and Mouser fields use distributor search URLs for the selected manufacturer MPNs so stock and packaging can be checked at order time.

Schematic

The KiCad schematic (ADE9000_Breakout.kicad_sch) implements Figure 55 of the datasheet with compact breakout constraints: only power and analog channels go to headers, while digital signals stay on test pads. Reference images and the datasheet are in docs/.

3D CAD

Project-local STEP models for all populated ADE9000 board parts are stored in models/step/. The PCB references these files through ${KIPRJMOD} so the 3D view and CAD export do not depend on a particular KiCad library installation.

The digital/debug header J1 uses SparkFun's staggered 1x16_Locking friction-fit footprint, vendored at footprints/SparkFun-Connector.pretty/1x16_Locking.kicad_mod from sparkfun/SparkFun-KiCad-Libraries commit 14865e2. It keeps the 2.54 mm header pitch but alternates pad positions by 0.127 mm so a standard breakaway male header can lock into the board without solder during bench use. The SparkFun library is licensed CC BY 4.0; attribution: SparkFun Electronics.

The stereo CT jacks use a black AP214-colored STEP model at models/step/Jack_3.5mm_CUI_SJ-3523-SMT_Horizontal.step, generated from the manufacturer SJ-3523-SMT-TR CAD ZIP in models/step/SJ_3523_SMT_TR.zip with scripts/create_sj3523_smt_step.py. The script bakes the DigiKey/Same Sky CAD into the KiCad footprint frame with the front barrel on the footprint's board-edge side, without adding artificial pad overlays. Do not substitute the through-hole SJ1-3523N model for this SMT footprint.

The voltage screw-terminal footprints use KiCad's 1x02 3.50 mm horizontal Phoenix STEP model as the closest installed mechanical equivalent for the 4Ucon footprint, with model-only offset (-1.75, -0.05, 0) to align the substitute body to the 4Ucon footprint outline.

A full board assembly STEP export is available at exports/step/ADE9000_Breakout.step. Regenerate it with:

& "C:\Program Files\KiCad\10.0\bin\kicad-cli.exe" pcb export step --force --subst-models --output "exports\step\ADE9000_Breakout.step" "ADE9000_Breakout.kicad_pcb"

Resources

License

This hardware design is released under the TAPR Open Hardware License v1.0. The PCB artwork includes a TAPR OHL notice on the back silkscreen.