Psu breakout

PSU Breakout v3 — the all-in-one bench PSU tool

Complete and fab-ready: 100 × 197.6 mm, routed, DRC-clean (0 violations / 0 unconnected at all severities), silkscreened. TB1/TB2 are rail-side hub members like AT/ATX/Molex (full pass-through, direct crowbar coverage); F7/F8 PPTCs (MF-RHT200, 2 A hold) guard TB2's −12V/−5V screws — the only high-energy polarity-swap directions — and D14/D15 are MBR20100CT TO-220 reverse clamps. Layout: connectors and SOURCE/PROT toggles in the north half, LOAD/PROFILE at the bottom corners, heatsink-bar frame holes as U-notch edge cuts, J16 ATX-in overhanging the top edge.

v3 unifies the whole family behind one board: the v1.0B breakout (ATX/AT/Molex/TB1/TB2/XV), the v1.1 switchable dummy loads, and the v2.2 rail generation + precision overvoltage protection.

The 5-control panel

Modes

Modes compose freely (load-test the generator, protected pass-through under load, …). The generator connect + enable share one throw, so a converter can never fight a PSU rail while isolated.

GEN-mode input scenarios

Everything generated runs off +12 V (GEN_PWR is fed from +12V_BANANA — the +12 banana post directly, or a PSU's +12 rail through F1). GEN engages all three generators at once: it fills missing rails; rails the source already has end up in parallel (∥) with the generated ones — benign for the unregulated negatives, contentious for regulated 3.3 V. The per-rail escape hatch is pulling that rail's blade fuse (F3/F4/F5), which splits the connector side (PSU) from the banana side (generator).

Footnotes: case 2 generates nothing because every converter runs off +12 V only (there is no 5 V → 3.3 V path); case 3 yields a complete set except +5 V — a bias/logic-experiment configuration, not a machine-powering one; case 1 needs the bench +12 channel's current limit set above converter overhead + startup inrush.

Blocks (all proven on previous boards)

• Breakout: ATX-in (right-angle 39300240 — the PSU cable plugs on), ATX-out (J18, Mini-Fit BMI 15-24-7240 — takes an ATX extension to the DUT), AT P8/P9 (36642-0001), disk Molex M/F (TE Mate-N-Lok), TB1 (5V/GND/12V/3V3-XV), TB2 (PG/−12V/GND/−5V), 10 banana posts, per-rail Keystone 3568 blade fuses, 7 red rail LEDs (R1–R7 left-to-right), XV = 9 V DC-only entry on the 3.3 V rail (unlike v1.0B/v1.1: D13's reverse shunt would dead-short an AC winding's negative half-cycles through an unfused loop — use v1.0B or v1.1 for C64-style AC bricks). D9/D10 (1N4148 LED clamps) are inherited from the AC-capable boards; with D13 holding the rail above −0.5 V they never conduct here and may be left unpopulated.
• Protection (v2.2): TL431B + 2N3906 + 2N6504 precision crowbars — +5 V trips 5.57 V, +3.3 V trips 3.68 V, +12 V trips 13.27 V — plus reverse shunts on every rail (SB540 on positives; MBR20100CT TO-220 duals on −5/−12 — non-sacrificial) and P6KE TVS clamps. A crowbar firing blows that rail's blade fuse. New in v3: the ARM/OFF gate-break switch.
• Loads (v1.1): RL1 47 Ω · RL2 10 Ω dual-role · RL3 10 Ω (3V3) · RL4 2.2 Ω on the return-bus scheme; SK 452 100 heatsink bar on top (holes x = 10/30/70/90) or drop-through backpack plate below; fan header (J17) for continuous PC-mode soak tests.
• Generation (v2.2): LM2678-3.3 buck (5 A ceiling — fit a 4 A blade in F3 when generating), A1212S-2W isolated −12 V with PPTC, 7905 linear −5 V from the generated −12 V (fleet-safe dependency: every machine that needs −5 V through these connectors also has −12 V).

Schematic

psu_breakout.kicad_sch — generated from the routed board by scripts/make_schematic.py (functional blocks, global net labels). Verified: the schematic's exported netlist matches the PCB pin-for-pin (278/278 netted pins, 0 mismatches) and ERC reports 0 issues. Custom symbols live in psu_breakout_sch.kicad_sym (registered via sym-lib-table). The board remains the source of truth — regenerate the schematic after board net changes.

Verification record

• SW2/SW5 footprints verified against the E-Switch prints ST141001 / ST131017 and the Taiway 100-TX drawing: pole pitch 4.83 [.190], rows 4.70 [.185], true body outlines (21.6/16.5 × 12.7). Holes are 2.3 × 1.4 mm plated slots (pads 2.6 × 1.7 oval, 0.15 annular = PCBWay min) sized to accept every termination style of the 100-series pattern: E-Switch M1 solder lug (2.03 × 0.76), M2 PC pin (Ø1.85 envelope), Taiway PC pins, and T90-clone type B lug (2.03 × 1.19) or type C pin. Orderable: SW2 = 1004P1T1B1M1QEH (lug, stocked), SW5 = 1003P1T1B1M2QEH (PC pin, stocked); M2/Taiway/T90 variants drop in.
• All 11 vertical-diode "A" silkscreen marks audited against pad nets: each sits at its diode's true anode (note: on D9/D10 the clamp cathode lands on the net named Dn_A — the LED's anode, not the clamp's).
• Trace widths audited per netclass. Deliberate under-class runs, all justified by actual current: SW2→F1 converter feed 1.6 mm (~1.6 A max), J6→RL1 snake 0.5 mm (0.26 A through 47 Ω), +5VSB spur 0.5/0.25 mm, −5V_TB spur and its −5V continuation past F8 at 0.85 mm (bounded by the PPTC's 2 A hold — trace rating matches the protector), and the +3V3 crowbar bias/trigger spur (R18/Q5 feed) at 0.5 mm (mA bias plus a millisecond gate pulse; the rail artery does not route through it).
• Final DRC: 0 violations / 0 unconnected, severity-all.

Assembly & bring-up notes

• Vertical diodes (D8–D18, D9/D10): body stands on the ringed pad, cathode band DOWN toward the board, folded-over lead into the hole marked "A". The ring only locates the body — the "A" is the polarity mark.
• Toggle levers: direction words on silk assume the standard lever-opposite-contacts convention and keyway-per-footprint insertion. One-time meter check at first assembly: lever north on SOURCE should buzz pad 11↔12 (GEN_PWR↔+12V_BANANA).
• Fuse guidance: F3 5 A (direct) / 4 A blade when generating; F2 up to 15/20 A for Lisa-class +5 V loads. Crowbar trips blow the rail's blade fuse.
• XV (TB1 pad 4, silk "3V3/XV"): 9 V DC-only entry riding the +3V3 rail. Never feed AC here: D13 (the +3V3 reverse shunt) conducts on every negative half-cycle — a dead short of the winding with no fuse in the loop (XV enters on the rail side). C64-style AC bricks belong on v1.0B/v1.1, which have no rail shunts. For DC keep PROT = OFF too if the brick exceeds the 3.68 V crowbar trip.
• PG (TB2 pad 1, net PWR_OK): meter the PSU's Power Good under test, or strap to the +5V screw when bench-feeding an AT board — without PG many AT machines hold themselves in reset.
• The four heatsink-bar frame holes are U-notch edge cuts (open-sided Ø3.2, retention lips preserved) — intentional, no fab note needed.
• Test AT/ATX units on PC profile (MICRO is too light a load for them). TB polarity-swap protection: the MBR20100CT clamps (D14/D15, tab = GND) hold a swap at ~0.6 V without damage, and the F7/F8 PPTCs in TB2's negative screws trip in under a second and self-reset — a swap ends with nothing to replace, even against a junk PSU. The same clamps cover the P8/P9-swap loop. Full analysis: RISK_ANALYSIS.md.