

This repository contains the complete design and implementation of a basic Phase-Locked Loop (PLL) circuit, referred to as PLL1.
- Size
- 51 × 54 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 15
- Nets
- 42
- Pads
- 88
- Tracks, vias
- 114, 0
- Pours
- 1
- Routed
- Yes
- KiCad
- KiCad 8.0 (file 20240108)
- Created
- 31 Jul 2025
- Updated
- 31 Jul 2025
Overview
Pll1 is an open-source printed circuit board by SohithTondepu, from the SohithTondepu/Phase-Locked-Loop repository on GitHub. It is a 2-layer board of 51 × 54 mm with 15 parts on 42 nets, routed with 114 tracks and 0 vias.
It is built around the LM324N, CD74HCT74E and CD74HCT86E, with the NE555P, BC557 and BC547 among its other parts. Its parts include 5 ICs, 3 capacitors, 3 transistors, 2 resistors and 2 connectors.
Main components
6LM324N
DIP-14-16V~-1.5V、1.5V~16V -40℃~+85℃ 1.5V~30V 250nA 35mA 4 50nA 600uA 7uV/℃ 80dB 9mV DIP-14 Operational Amplifier ROHSHGSEMIOperational AmplifierCD74HCT74E
PDIP-14-55℃~+125℃ 1 10pF 2 35ns@4.5V,50pF 4.5V~5.5V 4mA 4mA 4uA 50MHz 74HCT Series Complementary type D-Type Rising Edge Set and Reset PDIP-14 Flip Flops ROHSTexas InstrumentsFlip FlopsCD74HCT86E
PDIP-14-55℃~+125℃ 100mV、260mV 2 2V 2uA 3.98V、4.4V 32ns@4.5V,50pF 4 4.5V~5.5V 4mA 4mA 74HCT Series 800mV Push-pull TTL Compatible CMOS XOR Gate PDIP-14 Logic Gates ROHSTexas InstrumentsLogic GatesNE555P
DIP-80℃~+70℃ 100kHz 10mA 4.5V~16V DIP-8 555 Timers / Counters ROHSTexas InstrumentsTimers / CountersBC557
TO-921 PNP 100mA 100nA 150MHz 45V 500mW 6V 800 90mV、250mV PNP TO-92 Bipolar (BJT) ROHSDDFBipolar (BJT)BC547
TO-92Bipolar (BJT)Jiangsu Changjing Electronics Technology (CJ)
README
README.mdPLL1 PCB Project
This repository contains the complete design and implementation of a basic Phase-Locked Loop (PLL) circuit, referred to as PLL1. The project was developed using KiCad for schematic capture and PCB layout, and includes all the necessary files for fabrication and assembly. Before finalizing the PCB, the circuit was first tested on a perfboard to verify its functionality. Once validated, the PCB was fabricated and components were soldered manually.
Preview
Assembled PCB
Prototype Testing on Perfboard

Project Structure
PLL1-PCB-Project/
├── src/
│ ├── PLL1.sch # Schematic file
│ ├── PLL1.kicad_pcb # PCB layout
│ ├── PLL1.pro # KiCad project file
│ └── custom footprints/ # Custom footprint libraries
│
├── output/
│ ├── BOM.csv # Bill of Materials
│ ├── PickAndPlace.csv # Component placement data
│ ├── pll1.drl # Drill file
│ ├── *.gbr # Gerber fabrication files
│
├── media/
│ ├── pll1-real-board.jpg # Final PCB image
│ └── pll1-proto-board.jpg # Perfboard prototype image
│
└── README.md # Project documentationTools Used
- KiCad 8.0 – for creating the schematic and PCB layout
- Manual soldering – to assemble the fabricated PCB
- Perfboard – used for initial testing and verification of the circuit
Output Files
The output/ directory contains all necessary files for PCB fabrication and assembly:
- Gerber files
- Drill file
- Bill of Materials (BOM)
- Pick-and-place file
Applications
This project is intended for educational purposes and hands-on practice. It’s a simple yet effective way to understand the working of PLL circuits and gain experience in:
- Schematic and PCB design
- Manual soldering techniques
- PCB fabrication process
Parts
15| Qty | Value | Footprint | References |
|---|---|---|---|
| 2 | BC557 | Package_TO_SOT_THT:TO-92_Inline | Q2, Q3 |
| 2 | CD74HCT74E | pll flip:N14 | U3, U4 |
| 1 | 0.1uf | Capacitor_THT:CP_Radial_D8.0mm_P3.50mm | C3 |
| 1 | 0.1uf | Capacitor_THT:CP_Radial_D8.0mm_P3.80mm | C1 |
| 1 | 10nf | Capacitor_THT:CP_Radial_D8.0mm_P5.00mm | C2 |
| 1 | 2.2k | Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal | R1 |
| 1 | 2k | Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R2 |
| 1 | BC547 | Package_TO_SOT_THT:TO-92_Inline | Q1 |
| 1 | CD74HCT86E | xorfoot:N14 | U1 |
| 1 | Conn_01x02_Pin | Connector_PinHeader_2.00mm:PinHeader_1x02_P2.00mm_Vertical | J1 |
| 1 | Conn_01x03_Pin | Connector_PinHeader_2.00mm:PinHeader_1x03_P2.00mm_Vertical | J2 |
| 1 | LM324N | lm324foot:N14 | U2 |
| 1 | NE555P | Package_DIP:DIP-8_W7.62mm | U5 |
Questions
How big is the Pll1 PCB?
It measures 51 × 54 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Pll1 use?
15 parts, built around the LM324N, CD74HCT74E, CD74HCT86E and NE555P. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Pll1 KiCad files?
From the SohithTondepu/Phase-Locked-Loop repository on GitHub, at the commit this page was made from: the board is src/pll1.kicad_pcb and its schematic src/pll1.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the Pll1 design in my own project?
Its repository states no licence, so its author keeps all rights: ask SohithTondepu before reusing the design.
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