Sl56660

SL56660 — Bringing a Cray-1 Logic Chip Back to Life

The Fairchild SL56660 is one of the small set of logic building blocks the Cray-1 supercomputer (1976) was made of: a dual NAND gate (one 5-input, one 4-input) with complementary outputs, implemented in emitter-coupled logic (ECL) in a 16-pin ceramic flatpack.

I got one as part of the "First Super Computer" kit from Mini Museum — a lovely display piece for the bookshelf, but I missed some action. Since no datasheet, pinout or schematic for the part is in public circulation, I reverse-engineered the pinout from bench measurements and then designed a small demo board that lets the chip do again what it did in the Cray-1: switch.

Project status: the pinout is verified on real hardware, the board is fully designed and the ATtiny firmware is written (avr-firmware/) — but the board is not built yet, so the firmware has only been compiled, never run on hardware.

Reverse engineering the pinout

ECL cannot be probed like TTL: it runs on a negative supply (VEE = −5.2 V) with VCC at ground, the signal swing is small (≈ −0.9 V / −1.75 V, with the Cray using negative logic: logic 1 is the more negative level — that convention is what makes this OR/NOR hardware a NAND gate), and the outputs are open emitters that need external pull-downs. Applying power to the wrong pins would kill the die, so the pinout was recovered non-destructively first:

1. Unpowered mapping — every pin pair measured twice (diode-test mode and resistance mode), recorded as full 16×16 matrices. A ~36 kΩ star network converging on pin 12 exposed VEE and the nine inputs with their internal pull-downs; diode-conduction asymmetries separated the two VCC rails from the four open-emitter outputs.
2. Powered verification — current-limited bring-up, then dynamically driving each input to a valid ECL HIGH to resolve gate membership and output polarity.

The full write-up, including the measurement matrices, the reasoning behind each conclusion and the verified pinout, is in SL56660_reverse_engineering.md.

Verified pinout (summary)

Gate A is the 5-input NAND (inputs 1, 13–16), Gate B the 4-input NAND (inputs 8–11). Inputs have internal ~36 kΩ pull-downs to VEE (an open input floats to logic 1, which is neutral for a NAND); outputs are open emitters and need external pull-downs to VEE.

The demo circuit

The two NAND gates are cross-coupled into a classic bistable flip-flop (set/reset latch) — the exact role such gates played in the Cray-1. Around it:

• U102, an ATtiny4, generates the stimulus: SET and RESET pulses alternating at 1 Hz with 50 ms pulse width. The ATtiny runs between GND and VEE (its VCC on the board's GND rail), so an output driven high sits at 0 V; 8.2 kΩ series resistors (R102/R103) against the chip's internal 36 kΩ input pull-downs form a divider that lands the drive right in the valid ECL HIGH region without any dedicated level shifter. Between pulses the two pins go high-Z, so the ECL inputs fall back to their internal pull-downs — the firmware never drives them to VEE, and nothing fights a programmer on the shared TPI lines.
• D101/D104 (with 1.2 kΩ series resistors) show the SET/RESET pulses on the inputs.
• Q101 (BC856 dual PNP) level-shifts the two ECL outputs and drives the state LEDs D102/D103, so the latch changes state once per second — a full set/reset cycle every 2 s. The base dividers (8.2 kΩ/10 kΩ) place the detection threshold between the two ECL levels with comfortable margin on both sides, and all four LEDs run at a matched ~2.5 mA.
• R107–R110 (510 Ω) are the mandatory open-emitter output pull-downs to VEE; C105 decouples the supply at the package.
• D105, a 1N5819HW Schottky across the supply input (reverse-biased in normal operation), clamps an accidental polarity swap to a harmless ~−0.4 V — cheap insurance for a die that has been out of production for almost fifty years.
• J102, a 1.27 mm header, exposes the complete TPI programming interface of the ATtiny (TPIDATA/PB0, TPICLK/PB1, RESET, both rails), so the firmware can be flashed and updated in-circuit. Mind the rail naming when wiring a programmer: because the ATtiny lives between the board's GND (its VCC) and VEE (its GND), the programmer's VCC connects to the board's GND net and the programmer's GND to VEE.

Power comes in through J101: a single negative rail (VEE) against GND, as in the original machine. In practice an ordinary external 5 V supply does the job — connected with its positive terminal to the board's GND and its negative terminal to VEE, it yields VEE = −5 V, close enough to the nominal −5.2 V. The D105 clamp only survives what the supply can deliver, so use a current-limited supply (or a small polyfuse in the feed, e.g. 250–500 mA hold — the board draws only ~60 mA).

The board is deliberately tiny: it is meant to go back inside the Mini Museum display case together with the chip, fed through thin enamelled copper wires from the external supply, so the display piece keeps its looks but finally blinks.

Repository contents

License

This project is licensed under the CERN Open Hardware Licence Version 2 — Weakly Reciprocal (CERN-OHL-W-2.0). See LICENSE for the full text.

A word of caution

If you have one of these chips and want to repeat this: never apply power before you are sure of the supply pins. ECL parts are unforgiving — VEE on the wrong pin destroys the die instantly, and these dice stopped being made almost fifty years ago. Follow the unpowered-first method in the write-up.