2 layers54 × 40 mm
Sync buck
shonzinger-spec/ee-portfolio
Electrical engineering portfolio: simulated and verified EE projects (firmware, SPICE, KiCad, Wokwi) by Shon Zinger
37 partsMIT
2 layers75 × 50 mm
Power node
shonzinger-spec/ee-portfolioElectrical engineering portfolio: simulated and verified EE projects (firmware, SPICE, KiCad, Wokwi) by Shon Zinger
- Size
- 75 × 50 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 17
- Nets
- 42
- Pads
- 76
- Tracks, vias
- 65, 53
- Pours
- 4
- Routed
- Yes
- KiCad
- KiCad 10.0 (file 20260206)
- Created
- 27 Oct 2026
- Updated
- 4 Nov 2026
Overview
Power node is an open-source printed circuit board by shonzinger-spec, from the shonzinger-spec/ee-portfolio repository on GitHub, published under the MIT licence. It is a 2-layer board of 75 × 50 mm with 17 parts on 42 nets, routed with 65 tracks and 53 vias.
Its parts include 5 resistors, 3 capacitors, 3 connectors and 2 ICs. It belongs with the ESP32 boards of this library.
README
README.mdEE Portfolio - Shon Zinger
Electrical engineering projects by Shon Zinger, a York University EE graduate. Each project is fully virtual and reproducible with free tools: a standalone Python model runs with numpy and matplotlib only, and the simulation, schematic and firmware checks are documented with real output pasted into the project README. No hardware was built.
| # | Project | What it shows | Verification |
|---|---|---|---|
| 01 | Smart power-monitoring IoT node | ESP32 + INA219 power monitor on a 5 V / 2 A rail with an SSD1306 display: 50 mOhm Kelvin shunt, register-level driver, two-task FreeRTOS firmware | main.py self-check, LTspice and ngspice 6/6, host test 33/33, KiCad ERC 0 errors, PCB DRC + schematic parity 0 violations (check_pcb.py 13/13), Wokwi live run |
| 02 | Digital synchronous buck converter | 12 V to 5 V / 3 A, 200 kHz synchronous buck with discrete FETs, RC snubber and a digital PI loop in C (input and reference feed-forward, DPWM hysteresis, anti-windup, over-current latch) | main.py 59/59, LTspice vs ngspice cross-check, host test 19/19 + negative gate 4/4, KiCad ERC 0 errors |
| 03 | Ladder-to-DXF schematic generator | NEMA/JIC motor-starter ladder drawn from a device list: automatic device tags, wire numbers and coil/contact cross-references, DXF for any CAD program, BOM and wire list in Excel | main.py self-check, pytest 22/22, ezdxf audit 0 errors |
| 04 | Smart BMS simulator | 4S Li-ion pack: equivalent-circuit and thermal-runaway cell model, BMS firmware in C with OV/UV/OCD/SCD/temperature protection, coulomb-counting SoC, passive balancing and a cell-level end of charge | main.py 30/30, host test 34/34 + negative gate 6/6, ngspice 128 corners, KiCad ERC 0 errors |
| 05 | BLDC motor controller, hardware-in-the-loop | 24 V BLDC with Hall 6-step commutation: timer-interrupt PWM in C with firmware dead-time insertion, cascaded speed/current PI on a sampled DC-link shunt, over-current/Hall/stall protection, run against a switch-level inverter and motor model | main.py 26/26, host test 33/33 + negative gate 7/7, ngspice dead-time sweep and full inverter (within 1.5 % of the plant), KiCad ERC 0 errors |
Highlights of project 01:
- INA219 high-side current sensing: shunt sizing, PGA and calibration choices, saturation handling
- FreeRTOS on the ESP32: two pinned tasks, an overwrite-queue mailbox, a mutex-protected I2C bus
- KiCad schematic generated by script, checked with ERC and a netlist check
- Shunt front-end simulated in LTspice and cross-checked in ngspice
- Wokwi live run of the unmodified firmware against a custom INA219 chip model
Repository conventions
- A dedicated folder per project (
NN-name/). - A standalone main file (for example
main.py) that runs without a complex install chain. - A Verification section in each project README, with plots, logs and metrics pasted from real runs.
- A three-sentence Engineering why on the project's trade-offs.
- A Credits section stating what the author did and where AI assisted.
Author: Shon Zinger
AI assistance: Claude (Anthropic) helped with parts of each project; the Credits section of each project README says which.
License: MIT, see LICENSE.
Parts
17| Qty | Value | Footprint | References |
|---|---|---|---|
| 4 | MountingHole_3.2mm_M3 | MountingHole:MountingHole_3.2mm_M3 | H1, H2, H3, H4 |
| 3 | 100n | Capacitor_SMD:C_0603_1608Metric | C1, C2, C3 |
| 2 | 10 | Resistor_SMD:R_0603_1608Metric | R2, R3 |
| 2 | 2.2k | Resistor_SMD:R_0603_1608Metric | R4, R5 |
| 1 | 0.05 1% 1W | Resistor_SMD:R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm | R1 |
| 1 | 5V IN | Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical | J1 |
| 1 | ESP32-DevKitC-V4 | power_node:ESP32-DevKitC-V4_Socket | U1 |
| 1 | INA219AxD | Package_SO:SOIC-8_3.9x4.9mm_P1.27mm | U2 |
| 1 | LOAD | Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical | J2 |
| 1 | SSD1306 OLED | Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical | J3 |
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Questions
How big is the Power node PCB?
It measures 75 × 50 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Power node use?
17 parts. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Power node KiCad files?
From the shonzinger-spec/ee-portfolio repository on GitHub, at the commit this page was made from: the board is 01-smart-power-node/hw/kicad/power_node.kicad_pcb and its schematic 01-smart-power-node/hw/kicad/power_node.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the Power node design in my own project?
Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).