Pot pulse

Pot Pulse KiCad project

This directory contains the editable KiCad 9 project for the USB-powered Pot Pulse four-zone sensor node: first-pass schematic (issue #3) and first-pass PCB (issue #5).

Files

• pot-pulse.kicad_pro — KiCad project settings.
• pot-pulse.kicad_sch — editable schematic source of truth.
• pot-pulse.kicad_pcb — editable first-pass PCB (generated by build_pcb.py, routed via FreeRouter, DRC-adjudicated).
• lib/pot-pulse.kicad_sym — project symbols whose pin maps were transcribed from the manufacturer documents cited in ../component-selection.md.
• lib/pot-pulse.pretty/ — project land patterns (ESP32-C3-MINI-1, VEML7700) transcribed from the datasheets cited in ../component-selection.md; generated by generate_footprints.py.
• fp-lib-table / sym-lib-table — project library registration so the board opens on any machine with KiCad 9.
• generate_schematic.py — reproducible first-capture generator; the generated schematic remains editable in KiCad.
• validate_schematic.py — static acceptance checks for required parts, properties, nets, pin mappings, test access, and the native ERC summary.
• netlist_to_json.py — exports reports/pcb-input/{netlist,components}.json (placement/routing input data derived from the schematic netlist).
• build_pcb.py — generates pot-pulse.kicad_pcb through the pcbnew API (outline, placement table with courtyard/edge asserts, net classes, RF rule areas, pours, text).
• generate_footprints.py — generates the project land patterns from datasheet dimensions.
• route_driver.py — Specctra DSN export / SES import driver (import saves immediately before probing).
• dsn_strip_inner_layers.py — keeps the autorouter on F.Cu/B.Cu so the inner planes stay solid.
• rip_up_dangling.py / rip_up_zone.py / rip_up_congested.py — stranded-fragment and surgical rip-up helpers between router passes.
• close_stubs.py — deterministic final stub closer (collision-capsule tested; --dry reports LEFT pairs verbatim).
• fill_zones.py — headless "Fill All Zones".
• silk_hygiene.py — post-route silkscreen cleanup (hides dense-passive refs, shrinks TP/test refs, enforces 0.15 mm text stroke).
• reload_probe.py / check_placement_vs_table.py / board_inventory.py / list_plane_tracks.py / lane_blockers.py — verification probes (reload integrity, placement-vs-table drift, copper inventory, residual-gap diagnosis).
• reports/erc.rpt — native KiCad 9 electrical-rules report.
• reports/schematic-analysis.txt — supplemental static analyzer output.
• reports/pot-pulse.net — netlist export feeding netlist_to_json.py.
• reports/drc-placement.json — placement-stage native DRC (pre-routing).
• reports/routing/ — per-pass DSN/SES/DRC evidence; each passN-drc.json is the kicad-cli truth for that pass.
• reports/drc-final.json — committed final DRC state for pot-pulse.kicad_pcb.

Layout intent, keepout strategy, grounding approach, assembly/testability notes, and documented first-pass gaps: ../pcb-design-notes.md.

Reproduce and verify

The host needs KiCad 9 symbol libraries and Python 3.11+:

python3 -m venv /tmp/pot-pulse-kicad-venv
/tmp/pot-pulse-kicad-venv/bin/pip install -r hardware/kicad/requirements.txt
KICAD_SYMBOL_DIR=/usr/share/kicad/symbols \
  /tmp/pot-pulse-kicad-venv/bin/python hardware/kicad/generate_schematic.py
kicad-cli sch erc -o hardware/kicad/reports/erc.rpt hardware/kicad/pot-pulse.kicad_sch
KICAD_SYMBOL_DIR=/usr/share/kicad/symbols \
  /tmp/pot-pulse-kicad-venv/bin/python hardware/kicad/validate_schematic.py \
  --erc hardware/kicad/reports/erc.rpt

The PCB steps need the pcbnew Python bindings (KiCad container image); all scripts run inside hardware/kicad/:

kicad-cli sch export netlist pot-pulse.kicad_sch -o reports/pot-pulse.net
python3 netlist_to_json.py
python3 build_pcb.py                       # asserts courtyard/edge placement
python3 reload_probe.py                    # reload integrity + pad-net probe
python3 check_placement_vs_table.py        # board vs build_pcb.py table
python3 route_driver.py export reports/routing/passN.dsn
# host: java -Djava.awt.headless=true -jar freerouting-2.4.1.jar \
#   -de passN-2l.dsn -do passN.ses -mp 12 -gui.enabled=false   (after dsn_strip_inner_layers.py)
python3 route_driver.py import reports/routing/passN.ses
python3 rip_up_dangling.py && python3 fill_zones.py && python3 silk_hygiene.py
python3 close_stubs.py --drc reports/routing/passN-drc.json    # deterministic final stubs
kicad-cli pcb drc --severity-error --severity-warning --format json \
  --output reports/drc-final.json pot-pulse.kicad_pcb

The repository's headless kicad-cli wrapper runs KiCad 9 in a container. Committed reports are generated from the editable sources, not hand-authored.

Evidence boundary

Schematic files provide static schematic and native ERC evidence. The PCB provides static layout + native DRC evidence plus autorouter-derived routing provenance. These files do not provide simulation, assembled-board, EMC, environmental, field, or calibration evidence. RF keepout geometry is datasheet-derived; measured RF performance is bench evidence not yet claimed. USB full-speed impedance is not yet stackup-verified (documented gap in ../pcb-design-notes.md).