Clock

toy-dac

toy-dac started as a challenge: make a DAC that could at least produce sound. It has grown well beyond that proof of concept into a working DAC that reproduces music very nicely. The name is a nod to those humble beginnings, not a measure of what the project can do today.

A 1-bit ΔΣ stereo audio DAC implemented on a Xilinx 7-series FPGA (Digilent Cmod S7), driven from an I²S input.

The signal chain is entirely made-from-scratch RTL:

• I²S receiver with double-flopped synchronizers and AXI-Stream output
• External audio-family clocks — selects 22.5792 MHz or 24.576 MHz clocks for the 44.1 kHz and 48 kHz families
• Clock-domain crossing control — isolates housekeeping and sample processing in separate clock domains, synchronizing family changes and coordinating mute, pipeline reset, and clock settling
• Automatic input rate detection (32 / 44.1 / 48 kHz)
• Fractional-phase polyphase ASRC — 256 phases × 64 taps × 18-bit coefficients with 16-bit alpha lerp, single time-shared MAC, PI servo on the input ring-buffer fill — resampling onto an output grid at Fs_out = sclk / 64 (8× the nominal input rate)
• 2nd-order CIFB ΔΣ modulator (per channel) with TPDF dither, driving a single-bit differential output pin pair on each channel
• A small reconstruction filter and analog output stage on the carrier PCB

Internal test sources (silent, DC, 1 kHz DDS sine) and a bypass mode (raw I²S → modulator) are included for bring-up and characterisation.

The current build is surpassing 90 dB SNR. The remaining distortion is mainly the second and third harmonics (H2 and H3), which we believe are related to the DAC's switching output. Extensive listening tests have found it almost on par with commercial DACs, though there is still work to do on the finer details.

Status

First viable version. toy-dac has grown from a proof of concept into a working DAC capable of reproducing music very nicely. It has been exercised on hardware and through extensive listening tests, but is still evolving: the analog board is a hand-routed prototype, the design has not had formal verification, and there is more work to do on measured performance and subjective refinement. Module ports, parameter names, and pinouts may change without notice; treat it as an evolving project rather than drop-in IP.

Repository layout

fpga/toy-dac/   Vivado project (RTL under src/rtl, constraints under
                toy-dac.srcs/constrs_1, simulation under toy-dac.srcs/sim_1)
kicad/dac/      KiCad schematic + PCB for the analog carrier board
scripts/        Coefficient generation, simulation helpers, sanity checks
docs/           Block diagrams (top-level + ASRC internals)

Building

Open fpga/toy-dac/toy-dac.xpr in Vivado 2024.2, run synthesis + implementation + bitstream generation, and program the Cmod S7. The target part and pin assignments live in fpga/toy-dac/toy-dac.srcs/constrs_1/new/root.xdc.