Clock

Board 03: sequencer

The control unit: step counter, instruction and operand registers, flags, two decoders and the diode control matrix. 592 transistors, 354 resistors, 87 matrix diodes on 1035 crossings, 19 LEDs (counted on the routed board). The program counter and the return register are on the counter cards (D035).

How it runs an instruction (docs/isa.md):

• Steps are a one-hot ring of five flip-flops with asynchronous reset. S0 loads IR and the operand's low nibble (II); S1 counts (PCE); S2, only for a two-word instruction, loads the second word (OPI, PCE); S3 and S4 drive the matrix rows. The DONE column returns the ring to S0.
• IR and OPR are transparent latches open while their load line and PH1 are both high: they follow the memory word during the low half of the clock and are closed before the rising edge on which everything else changes.
• Decoders: IR3..0 to OP0#..OP15#, OPR3..0 to F0#..F15#, each through a pair of 2-to-4 predecoders so no NAND has more than two transistors in series.
• Rows: NOR(OPn#, T3N) for every opcode, NOR(OP0#, Fn#, T3N) for every family member, an S4 row for the four memory accesses, and for JC and JZ a second row that includes the latched flag; JNZ and JNC the same. 45 rows, 10k pull-ups.
• The matrix: a diode from a row to a column pulls that control line high while the row is active. 23 columns with 1 Meg pull-downs: 19 go to the bus header, PCL too, PCR and RAI to the link, DONE back to the step ring. New instructions are diodes; rows OP8..OP15 are free.
• Flags: CFQ and ZFQ latched from the ALU while FI and PH1.

Files

• sequencer.kicad_sch: generated by sim/build_sequencer.py from sim/sequencer.py. Do not hand-edit.
• fab/sequencer-assembly.svg: which crossing takes a diode and which resistor is not 47k (sim/assembly.py sequencer). On the board a crossing that takes a diode has a printed circle; the other 948 are bare pads.
• fab/sequencer-gerbers.zip: the eleven files the fab takes (four copper layers). python3 sim/order_check.py sequencer is the gate.
• sequencer.kicad_pcb, fab/: layout by sim/pcb.py. The matrix is laid out transposed: rows are vertical tracks at 3.81 mm pitch on the back, columns horizontal tracks at 10.16 mm on the front, a diode standing on each populated crossing.

Verification

The machine gate (sim/gate.py): the reference programs on the kicad-cli exports of ALU, registers, sequencer and counter with the hub, compared tick for tick with sim/emu.py. Results are recorded in the commit that adds the routed board.

D041 proof (2026-09-11): list.asm on alu, hub, registers, sequencer, counter and memory at the MIX corner, seed 3, the run that failed before the column buffers: 210 ticks, 0 mismatches (sim/out/d041_list_MIX3.log). Seeds 1 and 2 and the other programs are in the card gate.

Layout (D051, 2026-09-11, amended 2026-09-13): 245 x 255 mm on four layers, the tiles at the card pitch; layer 2 is a ground pour with a few routed tracks, layer 3 a third routing layer (two layers left the router about 100 nets short at this pitch and about 70 at 10.16 mm, D049). Routed with freerouting 2.4.1 (Java 25) with the layers ordered so that layers 3 and 4 route vertically and 1 and 2 horizontally, the power nets out of its network (the rails, stubs and vias are fixed copper) and the optimizer off. The matrix rows and columns are hidden from the router on the outer layers and a keepout fences the matrix, but the matrix diodes stay in the DSN with their pins off the nets, so layer 3 threads between their pads across it. Each matrix column tail ends on a fixed via 4.5 mm before the keepout with a short stub on layer 3, where the router picks it up on its vertical layer. The 45 row drivers stand under their matrix columns (three per tile column, left to right). The left field, 12 columns, is split: its right five columns start one tile row lower, leaving an 8 mm strip under the header's right half for the fan-out to pins 42 to 64, and the output buffers stand in the column under their own header pin; the 23 column buffers fill the columns beside the matrix, where the tails come out. The +5V feed runs along the top edge and down the right side of the board, never through the corridor between the left field and the matrix.

Routed board (2026-09-14, route v9): 0 unconnected, 0 DRC errors on the rules it was routed with (0.2 mm track, 0.15 mm clearance). The 132 warnings, read one by one on 2026-09-28: 59 dangling fixed stubs, by design (the 45 matrix column tails and the In2 stubs of the row tails the router did not need); 67 silkscreen overlaps (the printed circles of diodes on neighbouring crossings touch at 2.54 mm; two LED names touch a transistor's outline); 6 LED names clipped by a pad's mask opening (OPR0, OPR1, OPR3, OPR5, OPR6, ZFQ), which move in the silkscreen pass. One hand patch after the router, recorded in the plan (extra.patches) and applied by pcb.py: freerouting had hooked ENF across CFQ_m1 on layer 3 beside Q380. The SPICE export of this schematic is line for line the one the machine gate ran (resistor pin order aside): the tile mirroring of the re-placement is the only difference. Gate results on the card deck with this sequencer: all twelve programs at TYP, 0 mismatches (lfsr 1497 ticks, rerun with the virtual reset fixed in machine.py, sim/out/cards_lfsr_TYP.log); fib, alu, gcd, list, logic, call at LO, HI, MIX1 and MIX2: 24 of 24 runs, 0 mismatches (sim/out/gate_cards_corners.log); fib, list, logic, calc at TYP and LO with 500 pF per bus line: 8 of 8; fib and call with the clock card driving CLK: 0 mismatches (docs/cards.md step 9).