ElevatorLift

Hardware / KiCad Workspace

This folder is the hardware design workspace. The KiCad 10 project contains a Rev-A schematic capture and a routed four-layer PCB. The source board has passed its current KiCad routing checks, and the production archive contains the corresponding September 19 Gerber and drill outputs.

2026-09-19: sourcing changes (RV3032 RTC, active 4 MHz oscillator, three AC blade terminals and corrected TVS polarity) are present on the PCB and the post-rework KiCad DRC has no errors or unrouted items. The current production archive contains September 19 Gerber and drill outputs, and the current BOM/CPL contain the substituted references. Regenerate all outputs together only if the source board changes again. Follow the local rework and firmware handoff.

For JLCPCB, use the assembly exclusions and sourcing plan. assembly-policy.json controls owner-fit/bare-feature exclusions and verified catalogue corrections; tools/check-assembly-bom.py audits the original exports in production/ without changing them by default.

Files

Current Schematic Pages

1. Root hierarchy and design notes.
2. Power (Power_RevA).
3. MCU and storage (MCU_Storage_RevA).
4. VFD interface (VFD_Interface_RevA).
5. Encoder counter (Encoder_Counter_RevA).
6. Consolidated RF, field inputs and outputs (IO).

The superseded standalone RF, safety, output and connector child sheets were removed after their contents were consolidated into the active Rev-A hierarchy.

Rev-A Capture Assumptions

Use the hardware requirements matrix and the main README physical verification checklist as the source of truth. The current schematic assumptions are:

• Target PCB outline: 90 mm x 90 mm; corner mounting-hole centers 86 mm apart. The reported 12 mm underside and approximately 40 mm upper clearances are enclosure estimates, not defined keepout radii. Verify screw-head/standoff envelopes and the estimated 2.56 mm hole diameter before layout release.
• Main supply: fused 120 VAC + neutral to exact RECOM RAC10-12SK/277; schematic input tabs J20/J21/J22 are Keystone 1287 LINE/NEUTRAL/CHASSIS; protected 12 V distribution uses MF-MSMF075/24-2; 5 V uses R-78E5.0-0.5; and 3.3 V uses AP63203 with Bourns SRP7028A-2R2M. F40 remains 1.1 A hold, now 33 V; 25 W lighting is not qualified.
• RTC: U13 is RV-3032-C7 at 0x51, with primary-cell charging disabled and backup switchover requiring configuration. The PCB pin map and inhibited calendar firmware driver are updated; retention requires bench qualification.
• Counter clock: Y30 OT32254MJBA4SL active 4 MHz oscillator feeds U32 fCKi; fCKo is NC. C30 is 100 nF supply bypass; C31 is removed.
• 5 V source sharing: separate LM66100DCKR ideal diodes isolate the onboard 5 V converter and USB VBUS before they join the 5 V rail. USB VBUS alone does not power the separate 3.3 V regulator; an approved bench-power procedure remains necessary.
• VFD serial: the TXS0104E circuit matches the field design, with the TSW-104-07-G-S header ordered 5 V, GND, RX, TX. Assembled-board pinout and bench behavior remain release gates.
• Encoder: 12 V field inputs use 2.2 kOhm LED resistors into TLP291-4 isolation. This intentionally replaces the observed legacy 270 ohm values to avoid excessive optocoupler current; verify reliable switching on the actual encoder.
• RF: RXM-418-LR and LICAL-DEC-MS001 support is mandatory; include a separate wired LEARN interface plus a local service button/pads.
• Light output: protected 12 V MOSFET output with an onboard/external supply selector. The previous 750 mA lighting operated from the 10 W RAC10 supply; verify Rev-A load margin, and select the external 12 V lamp input if controller demand or upgraded lighting exceeds the onboard budget.
• Service station: J43 accepts dry-contact SERVICE KEY and HOLD-TO-RUN inputs with a shared GND; J44 accepts dry-contact SERVICE UP and SERVICE DOWN inputs with a shared GND. Use a maintained key switch and momentary controls. These are optocoupler-conditioned MCU inputs sharing controller GND, not an independent galvanic barrier or a safety-rated enabling circuit.
• Current MCU assignment: LIMIT_UP GPIO43/module pin 37 through 1k R62; LIMIT_DOWN GPIO44/pin 36; SERVICE_KEY GPIO3/pin 15. GPIO35/36/37 remain NC for octal PSRAM. J11 UART pins 3/4 are now NC; use native USB. Preserve active-low inputs and default JTAG eFuses; see the reset/boot details in the current handoff.
• GPIO42 is VFD_COMMS_ENABLE and connects only U24 OE plus R24's 10k pulldown. R25/U25/J25/TP26 and AUX R59/R60/Q41/F41/D42/J47 are removed. The separate external hardwired safety loop remains the required RUN authority, subject to VFD configuration verification.

PCB Preparation Status

• The current board contains 127 footprints (including four mounting holes) and 140 nets. The 90 x 90 mm outline runs from (97.26,52.29325) to (187.26,142.29325) mm. H1–H4 are plated 2.6 mm holes with 3.0 mm exposed copper pads on CHASSIS, retaining 86 mm spacing and a 2 mm offset from each adjacent edge. The custom footprint is ElevatorLift_Custom:MountingHole_2.6mm_Pad3.0mm_CHASSIS. CHASSIS remains separate from circuit GND.
• The board is routed and zones are filled. In1.Cu is the continuous SELV GND reference. In2.Cu is intentionally a mixed routing layer with GND fill because the board could not be completed within the available outer-layer routing area. This prototype decision is recorded in the routing and EMI plan.
• Net classes retain 3.2 mm mains clearance, 0.8 mm SELV power track width, 1.0 mm LIGHT_POWER track width and provisional USB differential-pair settings.
• The downloaded ESP32 module footprint contained invalid 0.2 mm plated holes. ElevatorLift_Custom:ESP32-S3-WROOM-1U-N16R8_CorrectedV2 replaces it with the correct perimeter geometry and nine symbol-compatible exposed-pad segments.
• The mains input uses separate Keystone 1287 LINE, NEUTRAL and CHASSIS tabs. The source board includes RV-3032, powered Y30 oscillator, revised TVS polarity and C31 removal; see the 2026-09-17 handoff for exact pin and purchasing changes.
• Current verification on 2026-09-19: ERC reports 0 errors and 35 warnings; PCB DRC reports 0 errors, 0 unrouted items and 120 library/mismatch warnings, with zero schematic-parity findings. The 227 pin/comms connectivity assertions also pass against the current export and live PCB pads.
• Owner review accepted the USB routing, mixed In2 routing, isolation clearance and physical-clearance decisions for this prototype. The library warnings are intentionally deferred; they must not be cleared by an uncontrolled footprint refresh.
• production/Elevator_Lift_Controller_A0.zip contains September 19 Gerber and drill files, while the BOM/CPL record RV3032, the Y30 oscillator, J20/J21/J22 mains tabs and C31 removal. Regenerate the complete package only if this source board changes again.

Dated review results are evidence, not a live release status. See the external-box review for the latest field-interface evidence and unresolved independent stopping authority.

Portable Project Libraries

Open ElevatorLift.kicad_pro, not an individual child sheet. Both project library tables use ${KIPRJMOD} paths:

• SnapEDA resolves to hardware/SnapEDA-Library.
• ElevatorLift_Custom resolves to the custom symbol file and footprint folder beside the project.

The repository-owned SnapEDA directory is a byte-for-byte copy of the imported download and includes the supplied STEP files. Standard KiCad libraries are still required, so install KiCad 10 with its normal symbol and footprint packages on the destination computer.

See field observations and the capture register for the confirmed observations, reusable-parts register, and the remaining release gates.

KiCad Tooling

This project is pinned to KiCad 10.0.4. Use tools\kicad.ps1 rather than a generic kicad-cli command so automated checks do not accidentally run against the also-installed KiCad 8 version.

# From the repository root
powershell -ExecutionPolicy Bypass -File hardware\tools\kicad.ps1 -Action Version
powershell -ExecutionPolicy Bypass -File hardware\tools\kicad.ps1 -Action Validate
powershell -ExecutionPolicy Bypass -File hardware\tools\kicad.ps1 -Action Gui

Validate writes KiCad-native ERC and DRC JSON reports to hardware\reports by default. The reports are generated design-review artifacts and should be regenerated whenever the schematic or board changes.

The helper scripts auto-detect conventional OneDrive/Documents KiCad plugin locations. On a different layout, set KONNECT_PLUGIN_ROOT to the installed Konnect directory and KICAD_10_BIN to the KiCad 10 bin directory. Neither environment variable is required merely to open and edit the project in KiCad. Use PowerShell 7 for the Konnect batch helper; the basic KiCad launcher also supports Windows PowerShell 5.1.