TEG

TEG — Thermal Energy Harvesting Prototype

Electronics for a thermal energy harvesting prototype: a small TEG array feeds a sub-1 V energy-harvesting front-end (BQ25504), which charges a buffer capacitor and backs up a regulated 5 V rail for a Noctua 5 V PWM fan and a test load.

Originally drafted on Flux.ai; this repo is the KiCad continuation, prepared for JLCPCB — made and assembled.

Status: the sub-watt board is complete, routed, DRC-clean and orderable — but it is now a REFERENCE, not the deliverable. REQUIREMENTS.md re-scopes the project to a fireplace-mounted, wedge-shaped harvester producing ~3–4 W with USB-A and USB-C output. At ~3–4 W the BQ25504 (max input power ≤ 300 mW) cannot be used, so a new power board is in design.

Decisions made (and why)

Settled — nothing here needs your input.

Remaining tasks — from here to a working prototype

Routing — done with FreeRouting

KiCad has no autorouter, so routing uses the standard SPECCTRA round-trip, scripted in scripts/freeroute.sh:

1. KiCad (pcbnew python) exports the board as a .dsn — outline, pads, nets and the net-class rules.
2. FreeRouting (external Java autorouter) routes it and writes a .ses session file.
3. KiCad imports the .ses back onto the board.
4. kicad-cli DRC verifies the result.

FreeRouting reported 0 unrouted, 0 violations on both its routing and optimisation passes, and KiCad's own DRC agrees: 0 violations, 0 unconnected. (It also does the rip-up-and-retry that a naive router can't — an earlier hand-written script in scripts/route_board.py reached ~95 % but never clean, so it was abandoned; it's kept for reference.)

Net classes

Set in scripts/gen_board.py and exported into the DSN so the router obeys them:

Why not wider power traces? Net classes are per-net, and the power/GND nets also land on U1's 0.5 mm-pitch pins, where a wider track cannot escape (0.3 mm already collides with neighbours) and the autorouter will not taper. At tens of mA, 0.2 mm is electrically ample. The classes still exist so wider widths can be set later, after a manual fanout from U1.

Fabrication outputs

Generated into build/fab/ (gitignored) by scripts/fab_export.sh — one command for the whole JLCPCB package (Gerbers + drill + BOM + CPL). Full flow and the ordering/approval path: docs/jlcpcb-fabrication.md.

⚠️ Check the CPL rotations before ordering. Position-file rotation conventions are a classic source of misplacement; compare TEG-pos.csv against KiCad's Fabrication Toolkit output (or JLCPCB's plugin) rather than trusting it blind.

Storage — what option D means

The BQ25504 needs some reservoir on VBAT (the datasheet's own reference shows ">100 µF"), and a 1000 µF 6.3 V SMD electrolytic (C970711) satisfies that: it holds the rail steady and is placed by JLCPCB.

But it stores ≈5 mJ, against ≈1.2 J for a supercapacitor. So:

• The fan cannot run from storage — it turns only while the TEG array supplies enough power directly (high ΔT). That is arguably the most informative first-prototype behaviour, but "fan runs for a few seconds off stored energy" is not a capability of this build.
• ⚠️ The electrolytic is polarised: pin 1 = +. Verify against the footprint silkscreen.

If you later want real storage, it's a one-part change: add a 0.22–0.47 F / 5.5 V supercap in place of C2 (hand-solder or via a 2-pin header), and optionally gate the MT3608 EN from VBAT_OK. The threshold network already suits a 5.5 V cell.

Parts — all verified in the JLCPCB catalogue

Sourced with scripts/jlc_lookup.py (JLCPCB's own parts API: id, library type, stock). Highlights:

Connectors & wiring

Wiring two TEGs in series (current 2-position J1)

TEG A(-) ──┬── TEG B(+)          # series junction, made off-board in the wiring
           │
TEG A(+) ──┴── J1 pin 1  (TEG+)
TEG B(-) ────── J1 pin 2  (TEG-)

Series doubles the voltage and leaves the current unchanged — which is what you want at low ΔT, where each module produces only a fraction of a volt. Parallel would double the current at the same low voltage instead.

⚠️ Limitation of the 2-position terminal: the series junction is made in the wiring, so the two modules cannot be measured independently at the board, and running the one-module baseline means rewiring the string. The plan asks to keep module leads accessible for independent measurement. A 3-position terminal (KF128-5.08-3P, LCSC C474953, in stock) would bring the midpoint onto the board — TEG_A+, midpoint, TEG_B- — making each module meterable and the baseline a no-rewire change. Roughly 5 mm wider, so it needs a placement nudge and a reroute.

Fan

There is no MCU on the board, so FAN_PWM (J2 pin 4) must be driven by an external source — a bench supply, signal generator, or your instrumentation. FAN_TACH (pin 3) has a 10 kΩ pull-up to +5V (R11) so you can read fan speed. Feed the fan from +5V (pin 2) and GND (pin 1).

Continuous validation

Every pull request runs these checks (see docs/validation.md):

Run the same checks locally with scripts/validate.sh (add --cad if KiCad is not installed). A failing CAD check usually means the committed exports are stale: run scripts/cad-run.sh and commit the updated artifacts.

What to expect when you test

Two TG12-4 modules produce only a few hundred mW at useful ΔT, while the fan draws ~0.5 W. With option D there is no energy store, so the fan will turn only while ΔT is high enough — it will not run continuously, and it will not run from stored energy. That is the expected behaviour of this build, not a fault.

Repo layout

Opening the project

Open hardware/TEG.kicad_pro in KiCad 7 or 8 (developed with KiCad 10). The library tables are already set up, so all parts appear under the TEG: nickname.

The schematic and board are generated — edit the part/net table in scripts/gen_schematic.py (and placements in scripts/gen_board.py) and re-run:

python3 scripts/gen_schematic.py   # -> hardware/TEG.kicad_sch
python3 scripts/gen_board.py       # -> hardware/TEG.kicad_pcb (unrouted, wipes routing)
./scripts/freeroute.sh             # route it (DSN -> FreeRouting -> SES -> DRC)
./scripts/validate.sh              # all checks (CAD artifacts + ERC/DRC)
./scripts/validate.sh --cad        # CAD artifacts only, no KiCad needed
python3 scripts/jlc_lookup.py "22uH inductor"   # search the JLCPCB catalogue

# one-command JLCPCB package: gerbers + drill + BOM + CPL into build/fab/
scripts/fab_export.sh              # see docs/jlcpcb-fabrication.md (ordering is manual + approval-gated)

Known cosmetic warnings (safe to ignore): ERC reports 3 × lib_symbol_mismatch on the two most recently fetched symbols (their embedded text is byte-identical to the library — an unresolved KiCad quirk), and DRC reports 1 × silk_overlap where the 8 mm electrolytic's reference text crosses its own silkscreen. Neither affects fabrication.

Tooling — JLCPCB parts

Two tools, for different jobs:

• scripts/jlc_lookup.py — finding parts. Queries JLCPCB's own API and returns id, library type (base = no setup fee / expand = extended) and stock.
• jlc-client — fetching a part's KiCad symbol/footprint/3D model by LCSC id, and appending symbols to the project library:

# Fetch symbol + footprint + 3D and append the symbol to the project library
JLC_API_TOKEN='<token>' jlc-client --symbol -l ./hardware/libs/TEG.kicad_sym \
    --footprint --footprint-lib TEG -o ./hardware/footprints C157471 C84817

Caveats learned the hard way (see PLAN.md §3):

• jlc-client's search is unreliable — as of 2026-10-10 it returns the same high-stock list for every query. Use jlc_lookup.py to search and jlc-client to fetch by id.
• jlc-client search --type ic also filters to one subcategory and hides power ICs.
• The component fetch endpoint is intermittent (Component … not found on EasyEDA/LCSC for everything, then recovers). Retry.

Design in one paragraph

Two Marlow TG12-4-01LS TEG modules in series feed the BQ25504 boost charger through a screw terminal. The BQ25504 does MPPT in hardware: R13/R14 sample a fraction of the harvester's open-circuit voltage onto a hold cap, and the chip regulates its input to that fraction — set to ≈50 % of Voc, matched-load MPP for a TEG. The charger holds a 1000 µF electrolytic buffer on VBAT and exposes VSTOR; an MT3608 boost then regulates a 5 V rail for the Noctua NF-A8 4-pin PWM fan (Tach pull-up, PWM from a test header) and a switchable 0.5 W test load (AO3400A low-side MOSFET). Two-stage on purpose: it keeps the harvester's MPPT decoupled from load transients and lets the buffer stabilise before the 5 V boost is asked to run.

Open questions and thermal/mechanical context: PLAN.md.