Devkyt

Kyttar Dev Kit

Open-source hardware carrier board for the Kyttar asynchronous DSP ASIC (SKY130 OpenFrame). The board hosts four Kyttar M.2 cards and plugs onto a ZTEX USB-FPGA Module 2.18b, giving a GNU Radio–driven development platform for the Kyttar array.

• © 2026 Lattrex Inc. — Board design by Chuck McClish
• Hardware licence: CERN-OHL-S v2 (Strongly Reciprocal)
• Project home: https://lattrex.com

What this board is

A passive carrier / breakout board:

• 4× Kyttar M.2 sockets (M1–M4) — MicroMod M.2 E-key sockets. Kyttar cards snap in; the sockets carry the x16 data port, x1 serial port, and resets. The four are wired as two daisy chains (M1→M2, M3→M4) plus per-chip breakout headers.
• 2× ZTEX 2×32 SMD headers (J1, J2) — mate the ZTEX USB-FPGA-2.18b's I/O connectors (rows A/B and C/D). All FPGA I/O, power (VIN/3.3V), and GND come through these.
• 6× 2×12 breakout headers (J4–J9) — expose each chip's signals and the daisy-chain link for probing.
• On-board Vcore supply — an LT3080 LDO (U1) fed from the ZTEX 3.3V rail, adjustable via trimpot (RV1), with a current-sense shunt (R1) and header taps (J3 = ISHUNT, J10 = VEXT for an external bench supply).
• 4-layer stackup: signals on top/bottom, a solid GND plane and power pours on the inner layers.

It is receive-capable SDR / DSP development hardware, not a finished product.

Repository layout

Only the KiCad hardware design is published here right now. The FPGA gateware and ZTEX SDK integration are coming later, once the bitstream-generation flow is complete (they're intentionally excluded — see .gitignore).

devkyt/
├── LICENSE                         CERN-OHL-S v2 (hardware licence)
├── README.md                       this file
└── devkyt/                         the KiCad project
    ├── devkyt.kicad_pro            project
    ├── devkyt.kicad_sch            schematic
    ├── devkyt.kicad_pcb            4-layer PCB (fully routed, DRC-clean)
    ├── devkyt.kicad_dru            custom design rules (PCBWay 4-layer)
    ├── fab_overrides_pcbway.txt    fab floor for the autorouter (PCBWay 4L)
    ├── fp-lib-table / sym-lib-table  project-local library tables
    └── libraries/                  custom parts + reference docs
        ├── footprints/devkyt.pretty/   Kyttar M.2 socket, GND standoff, logo
        ├── symbols/devkyt.kicad_sym     custom symbols
        ├── PARTS.md                     parts inventory + provenance
        ├── OPENFRAME_GPIO_MAP.txt        Kyttar gpio ↔ M.2 pad map (verified)
        └── ZTEX_HEADER_MAP.txt           ZTEX 2.18b header pin map + mirror rule

Not yet in the repo (coming later):

• fpga/ — FPGA gateware (the ZTEX↔Kyttar bridge / DDC).
• ztex/ — ZTEX SDK / firmware files.

Building / ordering the board

Fabricated as a 4-layer board (design rules target PCBWay; the .kicad_dru and fab_overrides_pcbway.txt encode PCBWay's 4-layer capability).

1. Bare PCB: export Gerbers + drill from devkyt.kicad_pcb (File → Fabrication Outputs). Order 4-layer, 1oz, 1.6mm, HASL. Board is ~150 × 90 mm.
2. Assembly: see the BOM in the KiCad schematic (Symbol Fields Table). Recommended split:
   • Have the fab place: the M.2 sockets (M1–M4) and the SMD pin headers (J1/J2, J4–J9).
   • Hand-solder yourself: the passives (C1–C3, R1, RV1), the LDO (U1), and the through-hole taps (J3, J10) — marked DNP in the BOM. These are 0805 / SOT / 0.1"-pitch parts that come on reels with high minimums; cheaper to buy a few from DigiKey and place by hand.

Key parts

Mates: ZTEX USB-FPGA Module 2.18b (bought separately).

Design notes

• Kyttar ↔ M.2 pad mapping and the ZTEX header pinout are documented in devkyt/libraries/ — both were verified against the ChipFoundry Caravel M.2 card netlist, the SKY130 OpenFrame datasheet/RTL, and the ZTEX pinlist.
• The M.2 socket footprint is adapted from chipfoundry/caravel_board (MicroMod M.2 E-key; underlying standard is SparkFun's, CC-BY 4.0).
• Orientation: the ZTEX headers mate the ZTEX board's bottom-side sockets; the carrier footprint is mirrored (row-swap) accordingly. See ZTEX_HEADER_MAP.txt.

Licence

Hardware is licensed under the CERN Open Hardware Licence Version 2 – Strongly Reciprocal (see LICENSE). If you make or distribute this hardware, or a modified version, you must make your design sources available under the same licence and keep the source-location notice (https://lattrex.com).