Frida65A

FRIDA: Fast Radiation Imaging Digitizer Array

This project focuses on improving analog to digital converters (ADCs) in CMOS image sensors, the chip design discipline with arguably the most stringent constraints on silicon design density. A design flow built on open source EDA tools enables comparison across different circuit topologies and process nodes including 180, 130, 65, and 28 nm. So far, we've fabricated a prototype ASIC in 65 nm using this methodology, which targets a state-of-the-art 2500 µm² area and 100 µW power budget, with a performance of 12-bit resolution at 10 Msps performance.

Frame-based radiation detectors with integrating front-ends are especially well-suited for applications like electron microscopy and X-ray imaging, where hit rates are high and spatial resolution should be maximized with simple pixels. This project also pursues a single-reticle array larger than 1 Mpixel with a continuous frame rate above 100,000 fps. To meet those array-level goals, the converter fabric must deliver aggregate throughput above 1000 Gbps while staying within a 1 W/cm² chip-bottom power-density budget and exceeding 5 ksps/µm² sampling-rate density. Successive-approximation ADCs are the primary architecture under study.

[!NOTE] FRIDA is still under active development. The repository is useful as a record of the design and flow, but it is not yet advertised as reproducible on other people's machines.

Progress

The initial prototype is designed in 65 nm and measures 1 × 1 mm. It contains 16 ADCs. The tapeout was submitted in October 2025, received March 2026, and is currently being characterized.

The fabricated FRIDA-1 ADC channel measures approximately 60.5 × 63.5 µm (about 3845 µm²):

The full FRIDA-1 chip, containing 16 ADC channels on a 1 × 1 mm die:

A micrograph of the fabricated prototype:

And the single-chip carrier test card, with wirebonded FRIDA ASIC:

Detailed command-line usage, build notes, and tool installation instructions are recorded in docs/usage.md.

Past Designs vs Current Target

The table below compares previous ADC designs with the current FRIDA target, highlighting improvements in resolution, speed, area, and energy efficiency. Notable advancements include higher conversion rates and lower power consumption per ADC, supporting the project's goal of scalable, high-performance digitizer arrays. The FRIDA column lists design targets; its 50 × 50 µm footprint is smaller than the fabricated FRIDA-1 channel shown above.