Cpld

Archived — final / last release. This project is complete and frozen. Issues and PRs are not expected; the tree is the historical record.

CPLD Development System

A hand-designed Altera MAX 7000AE/S CPLD development board and the digital labs built on it — from Lake Washington Institute of Technology Electronics 211 (2017–2018), by James Burney (K9DTV).

This repository packs the PCB design, fabrication outputs, board photos, project write-ups, and a Quartus calculator experiment that targeted the board.

Left (white / Ver2): board pictured with the MAX 7000S 5 V CPLD setup. Right (green): Ver1-style build.

What this board is

The goal was a durable printed CPLD trainer for the same class work that started on a hand-wired prototype: DIP switches in, dual hexadecimal TIL311-style displays out, on-board clock, and a standard JTAG/ByteBlaster programming header.

Two PCB revisions shipped:

Power: about 6.5 V–12 V input (prefer the low end; regulators get hot). Current-limit around 160 mA when using a bench supply. Drive each display decimal point with an open-drain buffer so the DP turns fully off.

MAX 7000S (5 V) vs MAX 7000AE (3.3 V)

Same PLCC-44 socket and the same lab/pin idea. The difference is supply voltage / family:

Same calculator logic / pinout in both folders — pick the build that matches the CPLD voltage on the board. Do not mix a 5 V part with a 3.3 V rail (or the reverse) without checking VCCIO/VCCINT wiring.

Supported CPLDs (PLCC-44):

• EPM7032 / EPM7032AE (32 macrocells) — display/switch / board-test labs
• EPM7064S (64 MC, 5 V) — full calculator (calulator/Calculator-full-5v/)
• EPM7064AE (64 MC, 3.3 V) — full calculator (calulator/Calculator-full-3v3/)

Repository layout

.
├── README.md
├── cpld-white.jpg / cpld-green.jpg   # Assembled boards
├── cpld-pcb.png / cpld-sch.png       # Layout / schematic views
├── PCB-files/
│   ├── cpld/                         # KiCad schematic + PCB (legacy KiCad 4 era)
│   └── CLPD-grb/                     # Gerbers + drill for fab
├── calulator/                        # Quartus II projects (folder spelling preserved)
│   ├── Calculator-full-5v/           # Full calculator — EPM7064S / 5 V
│   ├── Calculator-full-3v3/          # Full calculator — EPM7064AE / 3.3 V
│   ├── board test/                   # Board bring-up
│   ├── board-test-2/                 # Switch / display exercise (32 MC)
│   └── boardtest3/                   # Follow-on board test (uses board-test-2 BDFs)
├── project docs/                     # Word write-ups + markdown/ previews for GitHub
└── homework/                         # Class notes (ELEC 211 Ch. 4)

Folder and filename spellings (calulator, CLPD-grb, spaces in project docs) match the original archive on purpose.

Hardware pin map

DIP switches are active-low (closed = logic 0). Most designs invert them in the CPLD so “switch ON” reads as a 1 in the logic.

Programming-header pins follow the usual Altera JTAG layout (not duplicated in the table).

Major bill of materials (either revision)

Full Digi-Key / Mouser part numbers are in project docs/pcb document and cpld project.docx.

Labs and example designs

Documented in project docs/:

1. Board bring-up — display blank/latch behavior, 555 clock divider blinking both DPs (~1 Hz after ÷65536).
2. Priority encoder — exercises all DIP switches into the hex displays (BCD).
3. Calculator (needs 64 MC device) — mode select on SW11/SW12:
   • SW11=0, SW12=0 → min/max (7485-style compare; DPs show a swap)
   • SW11=0, SW12=1 → add
   • SW11=1, SW12=1 → subtract (borrow aware)
   • SW11=1, SW12=0 → multiply
     Full builds: Calculator-full-5v/ (EPM7064S, 5 V) and Calculator-full-3v3/ (EPM7064AE, 3.3 V).
4. Two-digit counter — final-style exercise on the same pinout (two digit counter cpld project.docx).
5. Hand-wired prototype — earlier 7000-series socket board used for Ch. 4 / Ch. 7 (211 build board.docx).

Quartus project (calulator/)

Intel/Altera Quartus II block-diagram labs. Folder name spelling calulator is preserved. The calculator top entity is named Calculator.

Full calculator (two voltage builds)

Each folder has its own Calculator.qpf, BDFs/BSFs, Calculator.pof, and reports. Ver2 display pins (latch_R=33, latch_L=36, Left_DP=31). Open the folder that matches the chip on the board.

Board tests

Suggested tools: Quartus II 13.0 SP1 (or 17.1 Lite) with a USB-Blaster.

KiCad / fabrication (PCB-files/)

• PCB-files/cpld/ — schematic (.sch), board (.kicad_pcb), netlist, project (KiCad 4-style .pro).
• PCB-files/CLPD-grb/ — Gerber layers (F/B Cu, mask, silk, edge cuts) and cpld.drl.

Open with a modern KiCad via the legacy importer, or send the Gerbers straight to a fab.

Documentation (project docs/)

Original Word write-ups stay in the folder (provenance). GitHub-readable Markdown previews (text extracted from those .docx files) live under project docs/markdown/:

Course context: Lake Washington Institute of Technology, Electronics 211, instructor Professor Peter Welty.

License / provenance

MIT -- see LICENSE. Personal educational hardware and reports by James Burney (K9DTV). Course homework notes in homework/ are included as archived class material. Altera/Intel tool output remains under their respective license terms.

Site / project page: k9dtv.com/project-cpld.html · GitHub: K9DTV/cpld-development-system

Archived from the original CPLD development-system materials (2017–2018) and published as a public K9DTV project.