SYNCHRO Zentrale

SYNCHRO System for Yielding Networked CHannel Rail Operation SYNCHRO is a modular, high-performance digital model railroad control ecosystem architecture based on the DCC (Digital Command Control) standard. Designed for robust deployment and high signal integrity, the system strictly separates timing and network logic from high-power distribution. Key design pillars include deterministic signal generation, total galvanic isolation to prevent ground loops, and autonomous hardware-level fault management.

System Architecture The ecosystem is decoupled into three primary hardware modules, allowing independent scaling of logic processing, track driving power, and distributed accessory control.

          +-----------------------------------+
          |      SYNCHRO_Zentrale (MCU)       |
          |  - Timing, Protocol & Networking  |
          +-----------------------------------+
                            |
                            v (Logic Signal / Differential)
          +-----------------------------------+
          |      SYNCHRO_Booster (Power)      |
          |  - Galvanic Isolation (6N137)     |
          |  - Power H-Bridge & Short Control |
          +-----------------------------------+
                            |
                            v (14V DCC Track Power)
          +-----------------------------------+
          |        SYNCHRO_Modul (Acc.)       |
          |  - Signal Monitoring & Decoding   |
          |  - Inductive Load Drivers         |
          +-----------------------------------+

1. Control Unit (SYNCHRO_Zentrale) The core processing hub handles the network stack, user interface routing, and precision generation of the digital DCC packet stream. It operates entirely on low-voltage logic levels with no direct track-driving capabilities to protect processing assets.

Core Processor: ESP32-S3 microcontroller utilizing its hardware Remote Control (RMT) peripheral engine. This configuration guarantees jitter-free, deterministic DCC bit-timing through dedicated hardware channels, leaving the dual-core CPU free to handle concurrent Wi-Fi, network protocols, and application layer connectivity.

Signal Integrity: Integrated high-speed bus drivers and differential level shifters (MAX485 / 74AHCT125) ensure noise-immune, differential transmission of the logic stream across longer cables to downstream power boosters.

Connectivity: Native USB-C interface providing USB-to-UART bridging for active monitoring, high-rate firmware flashing, and interfacing with industry-standard PC-based railroad command software.

2. Power Booster (SYNCHRO_Booster) The power-amplification stage isolates the sensitive low-voltage logic signals coming from the Control Unit, scales the voltage rail, and manages high-current output zones to safely drive individual track blocks.

Galvanic Isolation: High-speed 6N137 optocouplers completely break the ground loops between the upstream logic reference ground and the high-current track power ground, preventing destructive feedback currents.

Power Stage: Integrated Full H-Bridge driver (L6203 or discrete N-channel MOSFET bridge layout) optimized to switch high currents at standard track voltages (14V targeted specifically for N-scale layout compliance).

Autonomous Overcurrent Protection: A high-speed hardware-level short-circuit protection loop combining a precision low-side shunt resistor and an analog LM393 comparator. This safety mechanism achieves sub-millisecond latching shutdown independently of MCU firmware involvement, preventing thermal runaway during track shorts.

3. Peripheral Module (SYNCHRO_Modul) An accessory and function decoder designed to directly tap and monitor the active 14V DCC data stream from the rails, extracting configuration commands to actuate turnouts, mechanical servos, or signal arrays.

Logic Processing: Cost-optimized microcontrollers (ESP32-C3 or ATtiny architectures) coupled with an isolated input filtering stage optimized for reliable track-packet decoding under harsh electronic environments.

Output Driver: High-density, multi-channel Darlington/DMOS transistor arrays (TBD62083AFG / ULN2803A) equipped with integrated clamp diodes to safely absorb inductive flyback voltages generated by heavy turnout switch coils.

Interface Matrix: Universal pin headers and robust terminal blocks customizable via firmware configurations to run solenoid matrix turnouts, static LED signaling displays, or PWM-driven RC servos.

Repository Structure The directory tree is split logically into engineering domains to facilitate clean version control and modular updates via the graphical Antigravity 2 interface.

SYNCHRO/ ├── .gitignore # Top-level filter for KiCad/IDE artifacts ├── README.md # Core system documentation ├── git_universal_manager.ps1 # Antigravity 2 - Engine ├── Start_Universal_Git_Manager.bat # Antigravity 2 - Launcher ├── Datasheets/ # Electronic component documentation ├── Docs/ # System specifications and schematics ├── Software/ # Source code (Firmware, Apps) └── Hardware/ # Electronic Design Automation (EDA) ├── SYNCHRO_Booster/ # KiCad files for Power Booster ├── SYNCHRO_Zentrale/ # KiCad files for Control Unit └── SYNCHRO_Modul/ # KiCad files for Accessory Decoder

Hardware Development & CAD Rules All schematics and PCB designs are standardized on KiCad. To prevent repository bloating and synchronization conflicts, adhere strictly to the following tracking protocols:

Versioned Files *.kicad_pro — Project tracking configurations.

*.kicad_sch — Schematic design worksheets (modular sheet hierarchies are preferred).

*.kicad_pcb — Board layout designs (S-Expression plain text files optimized for line-by-line git diff operations).

Ignored Assets Local working state files (.kicad_prl), automated schematic backups (-backups/, *.bak), and local editor history configurations (.history/) are systematically excluded via the global .gitignore.

Production assets (Gerber photo-plots, NC drill coordinates, IPC-D-356 netlists, and structural 3D .step files) must be exported exclusively to isolated release packages or tracked explicitly via Git LFS if required.