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[ON PROGRESS] OpenStylophone-RP2040

Project Overview

The OpenStylophone-RP2040 is a standalone, open-source electronic musical instrument designed in KiCad. It pays homage to the legendary 1968 stylus-operated pocket synth while elevating every analog and digital subsystem to modern embedded audio engineering standards on a compact 2-layer printed circuit board ($151.0,\text{mm} \times 95.0,\text{mm}$).

Traditional stylophones relied on simplistic analog 555-timer / oscillator resistor-ladder networks prone to severe thermal drift, pitch instability, and harsh mono-tonal buzz. The OpenStylophone-RP2040 replaces that heritage with:

1. Digital Precision & Multi-Voice Polyphony: Driven by the Raspberry Pi RP2040 dual-core ARM Cortex-M0+ processor running at 133 MHz.
2. Audiophile-Grade Sound Generation: Texas Instruments PCM5102A 32-bit / 384 kHz stereo I2S DAC featuring an integrated ground-centered charge pump, coupled with a high-efficiency PAM8302A Class-D audio amplifier.
3. True Touch Stylus Keyboard: 24 gold-plated (ENIG) touch pads decoded via an 8-bit parallel-in/serial-out (PISO) shift register chain (74HC165), conserving MCU I/O down to just 3 GPIO pins.
4. Complete Portable Power-Path: Lithium-ion charging (TP4056), undervoltage/overcurrent protection (DW01A + FS8205A), seamless automatic USB/Battery power multiplexing (AO3401A P-MOSFET), and dedicated switching (FP6291 1MHz Boost) + linear (AP2112K-3.3 LDO) power rails.

[!WARNING] Prototype Status & Engineering Audit Notice (Rev 1.0 — Pre-Fabrication Phase):
This project is currently in the pre-fabrication hardware audit and remediation phase. While initial schematic capture and PCB routing were completed in KiCad 10, an in-depth hardware engineering peer review identified critical layout, sensing, and audio stage discrepancies (documented in Section 4). Physical fabrication is on hold pending the release of Rev 1.1.

Technical Specifications

System Architecture

The hardware architecture follows a strictly partitioned, modular pipeline designed to isolate high-current digital switching and boost converter ripple from sensitive analog audio references:

flowchart TD
    subgraph S1 ["Stage 1: Power Management & Battery Protection"]
        PWR["USB-C 5V VBUS / 3.7V Li-Po Cell"]
        CHG["TP4056 Linear Charger + DW01A/FS8205A Protection"]
        PPATH["AO3401A P-MOSFET Automatic Power-Path Switch"]
        REGS["Dual Power Rails: AP2112K-3.3 (Clean LDO) & FP6291 (5V Boost)"]
        PWR --> CHG --> PPATH --> REGS
    end

    subgraph S2 ["Stage 2: Human-Machine Interface & Touch Matrix"]
        KEYS["24-Key Stylophone Touch Keyboard (ENIG Solder Mask Opened)"]
        SR["3x Cascaded 74HC165 8-Bit Shift Registers (PISO)"]
        POTS["3x Analog Potentiometers (Vol / Cutoff / Decay) + Tactile Buttons"]
        KEYS --> SR --> POTS
    end

    subgraph S3 ["Stage 3: Core Processing & Synthesis Engine"]
        MCU["RP2040 Dual ARM Cortex-M0+ Core @ 133MHz"]
        FLASH["Winbond W25Q32JVSS 4MB QSPI Flash (Wavetables / Firmware)"]
        SYNTH["Hardware DMA / PIO State Machine (I2S Audio Engine)"]
        MCU <--> FLASH
        FLASH --> SYNTH
    end

Architectural Pipeline Breakdown

1. Stage 1 (Power & Battery Subsystem): Accepts 5V from USB-C or 3.7V from an internal Li-Po battery. The TP4056 manages battery charging while the AO3401A power-path MOSFET isolates the battery during USB connection. Regulated outputs include +3.3V (AP2112K LDO) for logic/analog audio and +5V_AMP (FP6291 Boost) for audio amplification.
2. Stage 2 (HMI & Sensor Acquisition): 24 gold-plated touch pads are pulled high via $10,\text{k}\Omega$ resistors. Contact with the grounded stylus pulls lines low, latched by three cascaded 74HC165 PISO shift registers. Potentiometers and push buttons feed RP2040 ADC and GPIO lines.
3. Stage 3 (Compute & Real-Time DSP): The RP2040 executes a polyphonic subtractive/wavetable synthesis engine. Core 0 handles user interface polling, I2C display updates, and MIDI parsing; Core 1 dedicates 100% of its cycles to real-time audio sample generation. PIO state machines drive DMA-buffered I2S transmission with microsecond-level determinism.
4. Stage 4 (Digital Audio Signal Chain): The PCM5102A DAC converts 32-bit I2S samples into ground-centered analog audio signals ($2.1,\text{V}_{RMS}$) with zero DC bias. Signals pass through differential DC-blocking capacitors into the PAM8302A Class-D amplifier.
5. Stage 5 (Acoustic Output & Normalling): The PAM8302A drives an internal 8Ω mini speaker. When a 3.5mm headphone jack is plugged into J5, integrated mechanical normalling contacts isolate the speaker, directing audio to external headphones.

Pre-Fabrication Hardware Engineering Audit & Remediation Log (Rev 1.0 -> Rev 1.1)

Prior to committing the board to physical fabrication, a comprehensive design audit was performed across the KiCad schematics, PCB layout, layer stackup, and netlist. This peer review revealed several electrical and geometric issues categorized below:

Critical Fabrication Blockers

[BLOCKER B1] Touch Pad Copper Polygons Overlapping (Dead Shorts on Keyboard Matrix)

• Finding: The 24 stylophone touch pads were created using raw graphical copper polygons (gr_poly) on F.Cu and F.Mask. Because KiCad treats raw graphical polygons without net associations as non-electrical geometry, Design Rule Check (DRC) failed to flag copper clearance violations. An algorithmic geometric bounding box audit revealed that adjacent pads overlap by $\approx 2.2,\text{mm}$ across 20 distinct pad pairs, shorting 24 discrete musical notes into 4 shorted islands.
• Root Cause: Drawing keyboard keys as graphical primitives rather than footprint-based netlist components.
• Remediation Plan (Rev 1.1):
  1. Remove all free-floating gr_poly elements from F.Cu and F.Mask.
  2. Create 24 dedicated KiCad footprint modules (Stylophone_Key_ENIG) with explicit net assignment (KEY1 through KEY24).
  3. Re-layout pads with a minimum copper-to-copper clearance of $\ge 1.5,\text{mm}$. To fit 24 keys comfortably across the $151,\text{mm}$ board width, layout will adopt a dual-staggered keyboard layout (12 lower natural notes, 12 upper sharps/accidentals).

[BLOCKER B2] DW01A Current Sense Disconnected & Overcurrent Protection Inoperative

• Finding: Pin 2 (CS) of the DW01A battery protection IC (U2) connects through resistor R8 ($470,\Omega$) to a dangling dead-end stub net (Net-(U2-CS)). Furthermore, the sources of the dual N-channel protection MOSFETs (Q1.6/Q1.7 of FS8205A) are tied directly to primary system ground (GND).
• Root Cause & Physics: DW01A detects overcurrent by monitoring the voltage drop across the low-side discharge MOSFET: $$V_{CS} = I_{discharge} \times R_{DS(on)}$$ With Pin 2 floating and the MOSFET sources tied directly to ground, $V_{CS} \equiv 0,\text{V}$. The overcurrent protection ($V_{OCP} = 150,\text{mV}$) and short-circuit protection ($V_{SCP} = 1.0,\text{V}$) can never trigger, creating a severe thermal and fire hazard during battery short-circuits. Additionally, $470,\Omega$ is $\approx 4700\times$ higher than appropriate for an inline current-sensing resistor.
• Remediation Plan (Rev 1.1):
  1. Separate battery negative (BATT-) from circuit system ground (GND).
  2. Place FS8205A dual MOSFETs strictly between BATT- and GND.
  3. Route CS (Pin 2) directly to BATT- through a $100,\Omega$ / $100,\text{nF}$ RC low-pass filter to monitor the combined $2 \times R_{DS(on)} \approx 25,\text{m}\Omega$ channel resistance per DW01A reference application note, tripping OCP at $\approx 6,\text{A}$.

[BLOCKER B3] PAM8302A Class-D BTL Directly Coupled to Grounded Headphone Jack

• Finding: The PAM8302A Bridge-Tied Load (BTL) differential outputs (OUT+ / OUT-) are routed through $100,\mu\text{F}$ electrolytic DC-blocking capacitors (C25, C26) straight to the Tip and Ring contacts of 3.5mm stereo jack J5, while the sleeve contact is tied to GND.
• Root Cause & Physics:
  1. PAM8302A is an unfiltered Class-D audio amplifier switching at $250,\text{kHz}$. A BTL output drives the speaker differentially without a ground reference.
  2. Connecting differential BTL outputs to a single-ended, ground-referenced headphone load forces high-frequency PWM square waves through external headphone cables (acting as efficient RF dipole antennas) and exposes low-impedance headphone voice coils ($16,\Omega - 32,\Omega$) to destructive carrier ripple.
• Remediation Plan (Rev 1.1):
  1. Restrict the PAM8302A output exclusively to the onboard 8Ω mini speaker via an LC low-pass reconstruction filter ($1,\mu\text{H} + 100,\text{nF}$).
  2. Route 3.5mm headphone jack J5 directly from the PCM5102A line outputs (AOUTL / AOUTR). The PCM5102A integrates a charge pump providing ground-centered, direct-drive $2.1,\text{V}_{RMS}$ audio capable of driving $32,\Omega$ headphones with audiophile clarity and zero DC-blocking capacitors.
  3. Use the switched contact of J5 to pull the PAM8302A SD (Shutdown) pin to GND when headphones are inserted, achieving silent, power-saving hardware speaker muting.

High Severity Engineering Observations

Medium Severity Quality & DFM Items

• M1 (74HC165 Serial Input Grounding): Pin 10 (SER) of the last shift register in the cascade (U7) must be tied directly to GND to prevent floating high-Z bits from shifting into the data stream.
• M2 (Crystal Oscillator Capacitive Tuning): RP2040 $12.000,\text{MHz}$ crystal circuit tuned for $C_L = 12,\text{pF}$ with $22,\text{pF}$ external load capacitors, compensating for package and PCB trace parasitic capacitance ($C_{stray} \approx 2-3,\text{pF}$).
• M3 (USB-C CC Pulldown Tolerance): Standardized R3 and R4 to $5.1,\text{k}\Omega \pm 1%$ metal film resistors to ensure 100% interoperability with USB-C PD smart chargers.
• M4 (ADC Input Filtering): Added $100,\text{nF}$ ceramic low-pass filtering capacitors on potentiometer wiper nets (ADC0, ADC1, ADC2) to suppress wiper contact noise and prevent aliasing.
• M5 (I2C Bus Pull-Up Optimization): Pull-up resistors R43, R44 validated at $4.7,\text{k}\Omega$ for $400,\text{kHz}$ Fast-Mode I2C bus rise times ($t_r < 300,\text{ns}$).
• M6 (Thermal Relief Geometry): Implemented thermal relief spokes on all component pad connections to the solid bottom ground plane to prevent cold solder joints during reflow.
• M7 (Test Points & Debug Accessibility): Added dedicated silkscreened test points for RP2040 Serial Wire Debug (SWCLK, SWDIO, GND) and critical power rails (3V3, 5V_AMP, VBAT).

Schematic & Circuit Subsystems

The schematic is organized in KiCad 10 across a 5-sheet hierarchical structure:

1. Root Hierarchical Overview

Provides high-level interconnection between power management, digital core, HMI inputs, and audio output stages.

2. Power Management & Battery Subsystem

• USB-C Interface (J1): Compliant CC termination resistors (R3, R4) for standard 5V/3A host detection.
• TP4056 Charger (U1): Configured with $2,\text{k}\Omega$ programming resistor (R5) setting charge current to $\approx 600,\text{mA}$. Dual LED indicators for charging (D1) and standby/done (D2).
• Automatic Power-Path (Q2, D4): The AO3401A P-MOSFET disconnects the Li-Po battery when USB 5V is present, powering the device directly from VBUS.
• AP2112K-3.3 (U4): Ultra-low noise 600mA linear regulator feeding logic and analog reference rails.
• FP6291 Boost (U3): 1MHz current-mode asynchronous boost converter generating +5V_AMP from battery voltage.

3. Processing Core, Clock & QSPI Flash

• RP2040 MCU (U5): Dual ARM Cortex-M0+ silicon with individual $100,\text{nF}$ decoupling capacitors on all power pins and a $1,\mu\text{F}$ cap on internal core regulator (VREG_OUT).
• Winbond W25Q32JVSS (U6): 32M-bit QSPI NOR Flash with $10,\text{k}\Omega$ pull-up (R14) and $1,\text{k}\Omega$ damping resistor (R13) on the QSPI_SS / BOOTSEL line.
• Oscillator (Y1): $12.000,\text{MHz}$ crystal with dual $22,\text{pF}$ C0G/NP0 load capacitors.

4. 24-Key Touch Matrix & HMI Controls

• Shift Register Cascade: Three 74HC165 ICs (U9 $\rightarrow$ U8 $\rightarrow$ U7) multiplex 24 touch pads over a 3-wire interface (KEY_DATA, KEY_CLK, KEY_LOAD).
• Pull-Up Array: Individual $10,\text{k}\Omega$ pull-ups hold all key lines at 3.3V until bridged to ground by the stylus.
• Analog Controls: Potentiometers for Master Volume, Filter Cutoff (R32), and Envelope Decay (R33) connected to RP2040 12-bit ADC channels.

5. Audiophile DAC, Power Amp & Display

• PCM5102A I2S DAC (U11): Hardware configured (SCK, DEMP, FLT, FMT to GND). Dedicated charge pump film caps produce ground-centered true bipolar output.
• PAM8302A Power Stage (U10): Low-noise differential audio input with $100,\text{nF}$ AC coupling capacitors (C27, C29).
• Headphone Jack (J5): CUI SJ1-3525N 3.5mm jack with switched normalling contacts.
• OLED Header (J4): 4-pin I2C connector with $4.7,\text{k}\Omega$ pull-ups on SDA (GPIO0) and SCL (GPIO1).

2-Layer PCB Layout & DFM Strategy

• Physical Dimensions: $151.0,\text{mm} \times 95.0,\text{mm}$ (Standard pocket synth format).
• Layer 1 (Top / F.Cu): High-speed digital signals, I2S audio traces, and power routing buses.
• Layer 2 (Bottom / B.Cu): Continuous, unbroken ground return plane providing low return-path loop inductance and shielding.
• Trace Sizing: Minimum $0.8,\text{mm} - 1.0,\text{mm}$ width for primary power trunks (+5V_AMP, V_SYS, VBAT, 5V_USB); $0.25,\text{mm}$ for high-speed digital buses.
• Noise Segregation: High-frequency switching circuits (FP6291 inductor and diode) are isolated at the top edge of the board, geographically separated from the analog audio section on the left.

Firmware & Software Architecture

The OpenStylophone-RP2040 is architected to support standard RP2040 embedded toolchains:

1. Dual-Core Asymmetric Multiprocessing (AMP)

• Core 0 (Control & HMI):
  • Hardware timer interrupt scans 74HC165 shift registers at $1,\text{kHz}$ (1ms debounce latency).
  • Reads ADC channels (Volume, Cutoff, Decay) using moving-average filtering.
  • Updates the 0.96" SSD1306 OLED display over I2C at $30,\text{FPS}$.
  • Handles USB MIDI Class compliant communication.
• Core 1 (Real-Time Audio DSP):
  • Computes 16-bit / 44.1 kHz or 32-bit / 48 kHz audio samples.
  • Polyphonic subtractive synth engine with resonant digital low-pass filtering.
  • Direct Memory Access (DMA) ping-pong buffer transfer to PIO state machine.

2. Supported Frameworks

• Raspberry Pi Pico C/C++ SDK: Maximum performance, bit-perfect I2S via hardware PIO state machines.
• Arduino-Pico (Earle Philhower Core): Direct support for Mozzi and Teensy Audio library ports.
• MicroPython / CircuitPython: Rapid synth prototyping using synthio and audiocore.

Bill of Materials

A complete, production-ready BOM with manufacturer part numbers (MPNs), LCSC part codes, and electrical tolerances is provided in docs/BOM.md.

License

• Hardware Design: Licensed under the CERN Open Hardware Licence Version 2 - Permissive (CERN-OHL-P-2.0).
• Documentation & Media: Licensed under Creative Commons Attribution 4.0 International (CC BY 4.0).

Designer & Contact

Designed with passion for open-source hardware, audio electronics, and embedded systems.

Veysel Turan
Electrical and Electronics Engineer

• Sakarya University of Applied Sciences (SUBÜ)
• LinkedIn: Veysel Turan
• GitHub: g210101021