E foc

e-foc — Hardware

A three-phase brushless (BLDC / PMSM) motor driver board designed to run the e-foc Field-Oriented Control firmware.

This repository contains the KiCad electrical design — schematics, project configuration and (eventually) the PCB layout — for the power and signal-chain hardware that the e-foc control software targets. The microcontroller itself lives on a pluggable module; this board provides the power stage, gate drive, current sensing, protection and peripheral connectivity around it.

Scope: this repo is the hardware. For the control algorithms (Clarke/Park transforms, Space Vector Modulation, current/velocity PID loops, auto-tuning), see the firmware repository.

Highlights

• Three-phase inverter built from three TI CSD88537ND 60 V dual NexFET™ half-bridge power blocks (one per phase) — low R_DS(on), sized for a 50 V bus at 5 A.
• FAN7888 3-phase gate driver with bootstrap high-side supply for clean, cross-conduction-protected switching.
• Low-side shunt current sensing (0.02 Ω) on each phase, amplified and filtered through a dedicated TLV9062 / TLV9064 analog conditioning stage for the controller's ADC.
• Wide-input switching power supply — LM5164 100 V synchronous buck plus AMS1117 linear regulators generating the +15 V gate-drive rail, +5 V and +3.3 V logic rails, with TVS bus-clamp protection (SMCJ51A).
• CAN connectivity via an SN65HVD230 transceiver for multi-axis / networked control.
• Non-volatile storage — 24LC04 I²C EEPROM (calibration / parameters) and W25Q32 32-Mbit SPI flash (logs / firmware assets).
• MCU-agnostic carrier — the controller plugs in over a 24-pin (2×12) header, matching the firmware's PlatformFactory abstraction (e.g. STM32F407 or TI Tiva TM4C1294 modules).

Board architecture

The design is organised as hierarchical schematic sheets, each a self-contained functional block:

Design requirements (spec)

These are the hard design targets the board must meet — the authoritative requirements used for design review and sign-off.

As-built component capability

D1 TVS sizing. The bus is 50 V max; the CSD88537ND is a 60 V FET. A standard TVS cannot both stand off 50 V and clamp below 60 V (clamp ratio ~1.5×), so SMCJ51A (Vrwm 51 V, Vbr ≥ 56.7 V, Vc ≈ 82 V) is chosen to absorb gross load-dump / inductive transients without conducting in normal operation. The 10 V FET margin against switching ringing must be held by layout — tight commutation loop, adequate bulk capacitance, and (if needed) an RC snubber — not by the TVS. Compliance with R1–R9 is confirmed during design review and bring-up.

Repository layout

e-foc/
├── hardware/                            # KiCad projects — one folder per board
│   ├── e-foc/                           #   main motor-driver board
│   │   ├── e-foc.kicad_pro
│   │   ├── e-foc.kicad_sch              #     top-level (root) schematic
│   │   ├── e-foc.kicad_pcb              #     PCB layout
│   │   ├── sym-lib-table
│   │   ├── components/                  #     project symbol libs (e.g. CSD88537ND)
│   │   └── schematic/                   #     hierarchical sub-sheets
│   │       ├── power-supply.kicad_sch
│   │       ├── driver.kicad_sch
│   │       └── … adc-conditioner, can-bus, encoder, eeprom-mem,
│   │             flash-mem, microcontroller-connector, serial-com
│   └── tiva-80pin-adapter/              #   EK-TM4C1294XL ↔ e-foc adapter board
│       ├── tiva-80pin-adapter.kicad_pro
│       ├── tiva-80pin-adapter.kicad_sch
│       └── tiva-80pin-adapter.kicad_pcb
├── scripts/                            # export helpers (run per board)
│   ├── export_review.py                #   review package  -> review_exports/<board>/
│   └── export_jlcpcb.py                #   fab + assembly  -> manufacturing/<board>/
└── .github/workflows/                  # CI: kicad-bot.yml (quality gate) + release.yml

Each board is a self-contained KiCad project in its own hardware/<board>/ folder — the .kicad_pro, root schematic and board share that folder (KiCad locates them by name and path). Hierarchical sub-sheets and project symbol libs are referenced by relative path within the board folder. Generated outputs are gitignored and land under review_exports/<board>/ and manufacturing/<board>/.

Getting started

This is a KiCad 10 project.

1. Clone the repository:

   git clone https://github.com/embedded-pro/e-foc-hw.git
   cd e-foc-hw

2. Open hardware/e-foc/e-foc.kicad_pro (or hardware/tiva-80pin-adapter/tiva-80pin-adapter.kicad_pro) in KiCad.
3. Open the schematic editor to browse the hierarchical sheets, or the PCB editor for the board layout.

Headless checks (the same ones CI runs)

With KiCad 8+ installed you can run electrical / design-rule checks locally:

kicad-cli sch erc  --output erc.json --format json hardware/e-foc/e-foc.kicad_sch
kicad-cli pcb drc  --output drc.json --format json hardware/e-foc/e-foc.kicad_pcb

Or use the export helpers (any board): python scripts/export_review.py for the e-foc board, python scripts/export_review.py --name tiva-80pin-adapter for the adapter; scripts/export_jlcpcb.py likewise for the fab/assembly package.

Continuous integration

Every push and pull request that touches a schematic or board file is checked by kicad-bot — a CI quality gate that wraps kicad-cli, KiBot, KiCost and KiDiff to run:

• ERC / DRC verification — electrical and design-rule checks.
• BOM availability — distributor stock / lifecycle (end-of-life) flags.
• Visual diffs — schematic & PCB change previews on pull requests.

The workflow lives in .github/workflows/kicad-bot.yml and uploads a kicad-bot-output/ artifact (report, metrics, raw violation data).

kicad-bot is a CI guardrail, not a substitute for design review or sign-off.

To enable distributor BOM pricing/availability, add the relevant API keys as repository secrets (MOUSER_KEY, DIGIKEY_CLIENT_ID, DIGIKEY_CLIENT_SECRET).

All third-party actions are pinned to a full commit SHA (with the version in a trailing comment) for supply-chain hardening.

Releases

Releases are automated with release-please and driven by Conventional Commits (feat:, fix:, …). The flow (.github/workflows/release.yml):

1. Commits to main keep an open release PR with the next version bump and CHANGELOG.md entries.
2. Merging that PR cuts a GitHub Release and tag.
3. On release, kicad-bot re-runs ERC/DRC (gating the release on a clean design), resolves the BOM, and produces Gerbers / drill / position files. These are zipped into e-foc-hw-<version>.zip and attached to the release as a downloadable fabrication package.

Version state is tracked in .release-please-manifest.json; behaviour is configured in release-please-config.json.

License

Released under the MIT License.