Power delivery

FPGA Cluster Framework

A scalable, FPGA-based cluster framework for parallel data acquisition and repeatable evaluation of hardware primitives (e.g., TRNGs, PUFs, and other custom bitstream-generating DUTs). The framework combines:

• Host-side automation (programming, orchestration, data collection, metadata logging)
• A synthesizable FPGA “shell” (control plane + high-throughput capture path)
• A pluggable DUT interface (drop in your TRNG/PUF/primitive and stream data into DDR-backed capture)

This repository is organized to include technical documentation, scripts, RTL, tooling, and PCB designs for the cluster setup.

If you are using this repository as part of a research portfolio, this README is written to be self-contained and reproducible for third parties who want to understand or rebuild the system.

Contents

• What this framework does
• Repository structure
• System overview
• Hardware prerequisites
• Software prerequisites
• Quick start
• Build flow
• Running a capture
• Integrating your DUT (TRNG/PUF/custom)
• Data format and metadata
• Reproducibility checklist
• Troubleshooting
• License and citation
• Contact

What this framework does

This framework is designed to make it practical to collect large, statistically meaningful datasets from hardware primitives across many FPGA instances, enabling you to:

• Run identical designs on multiple boards and compare results across devices
• Sweep configuration parameters and capture results consistently
• Log build + runtime metadata to support repeatable experiments
• Separate control and data responsibilities cleanly:
  • Control plane: programming, register writes, run control, status
  • Data plane: streaming capture into DDR via DMA (or equivalent)

Typical use cases:

• TRNG / entropy-source characterization and NIST compliance (throughput, bias, stability, robustness)
• PUF response collection across many devices
• Side-channel/physical-variation experiments requiring consistent capture workflows
• Automated regression testing of DUT changes

Repository structure

• documentation/ # PDF technical documentation and design notes
• fpga_cluster_fw/ # Folder containing the firwmare
• fpga_cluster_scripts/ # Host automation (programming, orchestration, data pulls, metadata)
• fpga_cluster_hw/ # FPGA design (shell + DUT interface + top-level integration)
• tools/ # Build helpers (TCL, Makefiles, environment setup, utilities)
• hardware/ # PCB / hardware design files for the Power Delivery and Communication interface

System overview

Conceptual architecture

Data path (capture pipeline):

• [DUT / TRNG / PUF] -> (stream) -> [FIFO/Adapter] -> [DMA/Writer] -> [DDR Capture Buffer] -> Host readout

Control path (orchestration):

• Host scripts program the FPGA, load firmware (if used), configure registers, start/stop capture, and retrieve data.

Design principles

• Pluggable DUT: DUT logic is isolated so you can swap primitives without rewriting the whole platform.
• DDR-backed capture: Enables high-throughput collection without requiring real-time USB streaming.
• Cluster automation: Host scripts should handle multi-board runs, retries, and consistent metadata.

Hardware prerequisites

This framework typically targets FPGA boards with:

• A Xilinx FPGA (e.g., Artix-7 class or similar)
• External DRAM (e.g., DDR3/DDR4) accessible from fabric
• A programming interface (typically JTAG over USB)

Update with your tested hardware:

• Board(s): Xilinx Artix 7
• Memory: DDR3
• Programming interface: JTAG
• Clocking: 100MHz (Adjustable)

Cluster setup notes (practical considerations):

• Use a powered USB hub suitable for the number of boards
• Ensure adequate power delivery and cooling
• Label boards (serial numbers / device IDs) to support reproducible tracking

Software prerequisites

Typical host environment requirements:

• Vivado (synthesis/implementation/bitstream)
• Vitis / XSDK (only if building embedded firmware; optional depending on design)
• Xilinx cable drivers (for JTAG)
• XSDB / xsct (common for scripted programming and debug)
• Python 3 (common for orchestration scripts)
• Common tools: make, bash, tcl

Tested tool versions (fill in):

• Vivado: 2023.4
• Vitis/SDK: [INSERT VERSION]
• OS: Linux/Windows
• Python: 3.11

Python requirements:

• scripts/requirements.txt

Quick start

1) Clone

git clone https://github.com/ddacot/fpga-cluster-framework.git
cd fpga-cluster-framework