Wattsense main

Wattsense main PCB - revision B, four copper layers

Updated 28 September 2026. This is the current four-layer candidate. Revision A remains separately available in ../wattsense-main/ as the two-layer budget alternative. Do not mix revision A and B manufacturing files or BOMs.

Revision B adds two continuous internal GND planes and 57 through-hole GND stitching vias. R4/R5 change to 2.2 kOhm after the I2C capacitance simulation. Connector positions, outline, core functions and current ceilings remain the same. The internal planes give outer-layer routes a ground reference; improved EMC, noise or thermal performance has not been measured.

One custom board is required for this version. It integrates three current monitors, the optional-load MOSFET, fuses, transient suppression, temperature/button interfaces and power distribution. The ESP32 board, 5 V converter, protected battery pack and matched charger remain external.

Status: engineering prototype, not physically validated. See reports/VALIDATION.md for the final design-check results. Fabrication files are for a first prototype; no hardware accuracy, thermal or reliability results are claimed.

Open and inspect

Open wattsense-main.kicad_pro in KiCad 10. Open its schematic and PCB from the project manager. All sources are editable; Python is not required to use them. The project-local symbol library is included. PCB footprints are embedded in the board and use the standard KiCad libraries.

What is designed

• 100 x 90 mm, four-layer FR-4, 1.6 mm nominal thickness, 1 oz outer / 0.5 oz inner copper. Stack: F.Cu signals/power, In1.Cu GND, In2.Cu GND, B.Cu signals/GND. See FABRICATION.md for stackup constraints.
• U1/U2/U3: INA219AIDR, SOIC-8, with 0.1-ohm 1 W shunts. Addresses 0x40, 0x41 and 0x44 respectively. This replaces the three breakout boards from the module-based shopping list.
• Battery/distribution path designed around 2 A maximum, with 1.5 mm main tracks. The required battery fuse and manual disconnect are external, close to the pack.
• External regulated 5 V input. F1 is a 2 A fuse; F2/F3 are 1 A branch fuses. Start with a lamp and a fan drawing no more than 0.6 A each. Keep total continuous 5 V current, including any ESP32 supply, at or below 1.5 A and verify temperature/current derating.
• AO3400A low-side fan switch, 330-ohm gate resistor, 47-kilohm hardware pulldown and SS14 flyback diode. A stopped controller defaults the optional output off when the GPIO is high impedance.
• Short cabled ESP32 interface, powered DS18B20 connector, two local-button connectors, four test points and four M3 mounting holes.
• Normally-open jumper JP1 for optional ESP32 5 V power. Remove JP1 before connecting ordinary USB power.

No additional custom BMS, solar-charger, mains or buck-converter PCB is required. These would add substantial development work without being necessary for the selected project objective.

Before spending money

1. Use the PCB BOM for the custom build; do not also purchase three INA219 modules or a separate fan-driver module.
2. Check the exact packages before substitution. In particular, INA219 SOIC and SOT-23 pin assignments differ, and a 0603 fuse does not fit this board's 1206 fuse pads.
3. Print the fabrication/assembly layout at 1:1 and check the purchased connectors, capacitor and IC packages against it. Compare substitute component drawings, not only product photographs.
4. Obtain delivered PCB and component quotes. The earlier project-wide Rs 9,500 allowance covered modules and does not establish the cost of this custom board. Buy battery-only hardware first; borrow/defer the solar panel if needed to keep the complete project below Rs 10,000.
5. Have the lab supervisor review the schematic and the selected pack/charger wiring before battery bring-up. This is an untested student prototype, so first power comes from a current-limited bench supply.

The five-day review should not depend on PCB delivery. Show the editable schematic, routed board, check reports and honest software demonstration while the prototype is being assembled.

Reproducibility

The one-time migration helpers in tools/ refuse to repeat their migration. The native schematic/PCB are the deliverables; edit these in KiCad. After any manual edit, rerun check_and_export.ps1, regenerate previews and repeat the physical checks affected by that change. Full-system and reduced SPICE simulations are in the project-root simulations/ folder, with assumptions and results in docs/SIMULATION_REPORT.md.

No board has been ordered, no components have been purchased and no payment has been made.