BP16

ADS7057 test board (low-power 3.3 V version, v3)

The middle step between the perfboard and the AFE PCB. It takes the signal from the sensor, filters it, digitizes it with the ADS7057, and gives the SPI bus and two listener lines to a ZedBoard PMOD port. It is powered only from the PMOD 3.3 V. There is no USB and no regulator.

The 5 V / USB-C revision is kept in the git tag v2-usb-5v.

There are two boards, ordered separately:

The head connects to SENSOR IN (J1) with one coax cable. The coax carries 3.3 V to the head (a bias-T) and the signal back. To use a function generator instead of the head, cut JP1.

The board is a narrow strip (21.5 mm) so that boards fit on adjacent PMOD ports (pitch about 22.7 mm). It is always on: the whole chain and the listener run all the time, and the listener only observes.

What changed from v2 (5 V, USB-C)

Uses

The board serves two purposes. In the plant experiments, four boards sit on ZedBoard PMODs JA to JD: two control plants, one drying plant and one reference sensor. Each board is one channel. The listener lines tell the FPGA, next to the full waveform, how often a burst crosses a small or a large threshold. That data decides whether the battery product can run on a listener alone.

Circuit

Main board: 125 × 21.5 mm, 2 layers, all SMD parts on top, GND pour on both layers, 786 + 100 tracks.

Sensor head

The perfboard circuit (TRL3 schematic), on its own board:

The bias-T at 3.3 V costs 0.17 dB at 250 kHz and 19 dB at 10 kHz (python3 sim/head_bias_t.py 3.3). The board is 22 mm long, not the 20 mm of the capsule drawing v3.

Two head amplifiers. The OPA365 is the lab default: it keeps the waveform faithful (noise gain 35 gives 1.4 MHz bandwidth) but draws 4.6 mA. The OPA314 draws 150 µA and fits the battery goal, but its 3 MHz gain-bandwidth needs Cf 220 pF (−3 dB near 360 kHz) and it has 14 nV/√Hz of noise against 4.5. Both are SOT-23-5 with the same pinout. Swap the amplifier and Cf.

Silkscreen

Reference designators (R1, C4 and so on) are on the F.Fab layer, not on the silkscreen. Open the KiCad file to see them.

Power

All power comes from the ZedBoard PMOD. J3 pins 6 and 12 carry 3.3 V and pins 5 and 11 carry GND. The ZedBoard feeds the PMOD connectors from its 3.3 V rail, rated 3 A and shared with the FMC and the other PMODs. This board draws about 27 mA, plus 5 mA for the head, so four boards are about 130 mA. Feed J7 instead (and cut JP6) to run on the bench.

J7 is a 5-pin header: 1 Onboard + (PMOD 3.3 V), 2 Force +, 3 Sense +, 4 Sense −, 5 Force −. Pins 2 and 3 are the board rail, pins 4 and 5 are ground. A jumper from pin 1 to pin 2 powers the board from the ZedBoard. To power it from a source-measure unit (for example a Keysight B2901BL) remove the jumper and connect Force to pins 2 and 5 and Sense to pins 3 and 4. The SMU then measures the total board current. JP3 (closed) joins the capture rail: open it to feed or switch U1, U2, U3 and AVDD separately. JP1 is the head power link.

AVDD is the ADC reference, and full scale is ±AVDD. It comes from the rail through 10 Ω and 10 µF. The ZedBoard 3.3 V noise is not known yet: probe TP11 and TP12.

The long-term product runs from a battery for a year. This board is the lab version. The listener (about 25 µA) and the OPA314 head (150 µA) are the building blocks for that, and the plan is in doc/lowpower_plan.md.

Through-hole parts

JLCPCB solders these. They are in the BOM and the pick-and-place file.

If JLCPCB declines a through-hole part, delete its line from the BOM and solder it yourself. The board has the same footprints either way.

Connectors

• J1 SENSOR IN: SMA for the sensor head, carries +3.3 V on the centre pin (JP1 bridged).
• J4 SCOPE OUT: SMA monitor output, LPF_OUT through 51 Ω.
• J7 header: power and 4-wire SMU connection (jumper 1-2 for the PMOD supply).
• H1, H2: M3 mounting holes.
• J3 PMOD: 1 CS, 3 SDO, 4 SCLK, 5/11 GND, 6/12 3V3, 7 BIG_N, 10 WAKE_N.

All device ports are SMA female. Use one cable type everywhere (SMA male to male, RG316 or RG174, short): head to SENSOR IN, SENSOR IN to a generator, SCOPE OUT to the oscilloscope through an SMA male to BNC female adapter. The RP-SMA parts in some shops do not mate with these jacks. Connect the head to the oscilloscope only through the board, since the bias-T that powers the head is on the board.

Before you plug the board into JA–JD, check that pins 5/6 and 11/12 line up with GND/VCC on the ZedBoard silkscreen. Adjacent ports are about 22.7 mm apart and the board is 21.5 mm wide.

SPI

• CS falling edge starts a conversion.
• Read 18 SCLK cycles on SDO. The frame is a leading 0, then D13..D0, then zeros (datasheet Fig. 1).
• Each frame returns the result of the previous conversion. The first frame after power-up returns all zeros.
• After power-up, send 24 SCLKs in the first frame. That starts the offset calibration (datasheet 8.4.3.1), and SDO stays at zero. Then wait at least 95 ns before the next CS fall.
• Repeat the calibration when AVDD or the temperature changes a lot.
• SCLK can go up to 60 MHz. Start at 10–20 MHz.

Cost (JLCPCB Economic PCBA, shipped to Chile)

The two boards are two JLCPCB orders (or one checkout with two designs). python3 hw/tools/cost.py prints the model. It is calibrated on the real quote of the first revision (2026-10-12, 5 boards, $114.36, no bias-T). The new parts have list prices from the JLCPCB library of 2026-10-15. The v2 numbers are estimates until you upload the files.

Both orders together, with shipping (Global Standard $10.75 per parcel) and 19 % IVA:

• The head's fixed fees (setup $8.24, stencil $1.55, hand-solder labor $3.61, PCB $4.00, one more extended type) are about $20 per order. A single panel would save them, but it forces equal quantities and mouse-bite tabs. Two orders let you buy 2 ADC boards and 10 heads.
• The OPA365 ($2.67) is the most expensive part of a head. The OPA2365 (SOIC-8) would be $1.38 and needs no new extended fee, but it does not fit in 10 mm × 27 mm with the SMA.
• DHL Express costs about $32 more per parcel (3–7 days).
• "Confirm Parts Placement" adds $0.45 per order.

First revision, real quote for 5 boards (no head, no bias-T):

The ADS7057 pays no X-ray fee in Economic assembly. The through-hole part types (SMA, headers, trimmer) pay no extended-part fee.

The model is calibrated on the first quote. A real quote of this revision (2026-10-15, 5 ADC boards, 5 heads, one checkout) showed merchandise $159.73 and shipping $52.45 because the cart was above $150. Split it in two orders (Global Standard $10.75 each) to stay below that line.

JLCPCB placement check

The JLCPCB viewer showed four problems on the first revision, and the CPL corrects them. New parts are not checked yet: U6 and U9 (TLV7022, SOT-23-8), U8 (SOT-23-5, head), L1 and L2 (1210 inductors), J6 (SMA). Look at them in the viewer.

J3 and J7 have their origin on pin 1 in the KiCad footprint, so they are placed by that pin.

Verification

sim/vendor_chain.py runs the checks and sim/vendor_results.txt holds the output. The OPA365 is TI's own model. The THS4531 is a datasheet-based model (27 MHz, 2.5 Ω), because TI's model gives a −3 dB point at 17 kHz in ngspice. The ADC input is the datasheet model: 50 Ω and 16 pF per leg. Run python3 sim/models/fetch_models.py to download the TI models, which are not stored in the repo.

Things the simulation does not cover:

• THS4531 stability with the 400 pF load. TI's guidance is a 2 pF differential load without an isolation resistor, so 20 Ω and 400 pF needs a measurement. If it rings, raise R16 and R17 from 10 Ω to 20 or 30 Ω.
• Temperature and the noise of a real power bank.
• Layout coupling and the real ZedBoard supply.

Paper checks:

• The chain was simulated at 3.3 V (sim/vendor_chain.py, sim/g1_chain33.py).
• The board draws about 27 mA plus 5 mA for the head, about 0.1 W.

Bring-up

With the sensor head: connect it to J1 with the coax, power the board from the PMOD (or J7 at 3.3 V), and the head runs from the rail (about +4.3 mA). Measure about 2.9 V on C37 and 1.45 V on the OPA365 output, VREF and C35. Then continue from step 3.

1. Remove the J7 jumper and feed pins 2 and 5 with 3.3 V and a 100 mA limit (SMU Force), Sense on pins 3 and 4. Check +3V3 (3.30 V), AVDD (3.30 V), VOCM (1.65 V), VMID5 (1.65 V) and REFL (1.65 V) at the test points before the PMOD connects. Then fit the jumper 1-2 and connect the PMOD.
2. Plug the board into the ZedBoard and check that WAKE_N and BIG_N read high (3.3 V).
3. Feed J1 from the Analog Discovery 2 with a 250 kHz, 100 mV sine. Compare SCOPE OUT with the input on the scope (1 MΩ input).
4. Read SPI codes. Check the idle code and the amplitude against the scope.
5. Sweep 10 kHz to 2 MHz and compare with the table above. The 10 kHz loss is the thinnest margin.
6. Raise a 250 kHz burst from 10 mV: WAKE_N must drop near 35 mV and BIG_N near 111 mV at J1 (±12 mV from the comparator offset). Log TP15 to TP18 on the scope.
7. With the SMU on J7, read the total current (about 25 mA). Open JP3 to read the capture chain and the listener separately.

Manual (doc/)

doc/ADS7057_test_board_hardware_manual_letter_v0.3.pdf explains the boards in 54 steps plus the sensor head: the basics, every block, the layout, the order and the bring-up. Two print versions (_print, _print_duplex) have a 14 mm binding margin.

Rebuild: M4_PDF_PYTHON=<python with pymupdf> python3 doc/tools/make_adc_manual.py. The figures read doc/data/board.json and doc/data/sim.json, made by doc/tools/export_board.py (KiCad python) and doc/tools/export_sim.py.

Files (hw/)

• ADC_Test.kicad_pro/.kicad_sch: the KiCad 10 project and the schematic of both boards.
• ADC_Test.kicad_pcb: main board. ADC_Head.kicad_pcb: sensor head. Both are built from the same netlist.
• ADC_Test_schematic.pdf: the schematic.
• fab/ADC_Test_gerbers.zip, fab/ADC_Head_gerbers.zip: Gerbers and drill files.
• fab/ADC_*_BOM_JLC.csv and fab/ADC_*_CPL_JLC.csv: BOM and pick-and-place for each board.
• preview/: renders and the 1:1 print PDFs of both boards.
• DRC: main board 0 errors and 0 unconnected (the parity warnings are the head parts, which are not on this board). Head board 0 unconnected, two courtyard warnings.

Rebuild

python3 hw/tools/design.py hw          # schematic (then export netlist with kicad-cli)
NOPLANE=1 FREEROUTING=/path/to/freerouting hw/tools/route.sh 60   # place (layout_v3.py), route, finish
BOARD=head FREEROUTING=/path/to/freerouting hw/tools/route.sh 60   # the sensor head
hw/tools/drc.sh; BOARD=head hw/tools/drc.sh
hw/tools/fab.sh && BOARD=adc python3 hw/tools/jlc_files.py && BOARD=head python3 hw/tools/jlc_files.py

Freerouting 2.4.1 needs Java 25 (the macOS .dmg bundles it).

At JLCPCB checkout

• Two orders: upload ADC_Test_* and ADC_Head_* separately.
• Upload the new CPL, then open Component Placements and check U6, U9 (pin 1), J7 and J3 (see "JLCPCB placement check"). On the head also check U8 pin 1, L1, J6.
• Look at J1, J4 and J6 as well. The SMA model looked offset against its four legs.
• Check pin 1 of U4 (ADS7057) in particular.